Linear Switch Circuit Thermal Runaway Protection
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Solution Overview
Problem
As IC technology advances towards miniaturization, power field-effect transistors (FETs) face increased vulnerability to thermal runaway due to limited safe operating area (SOA), particularly in low on-resistance FETs used in linear switch applications, where thermal runaway can lead to device damage and unpredictable failure.
Innovation Solution
A system comprising a first power FET and a second power FET in parallel, where the second FET is smaller and has a higher on-state resistance, is used to manage current flow during drain-to-source voltage (VDS) saturation conditions, with a control circuit adjusting drive signals to redirect current from the first FET to the second FET and employing a thermal sense diode aligned with the second FET to detect and prevent thermal runaway.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single large power FET is used to achieve low on-resistance, then current carrying capability is improved, but vulnerability to thermal runaway increases due to limited safe operating area
Solution Approach 1:
The patent divides a single large power FET into multiple parallel power FETs (first power FET and second power FET). This segmentation allows the current to be distributed across multiple devices, reducing the current density and power dissipation in each individual FET, thereby reducing thermal runaway vulnerability while maintaining the overall low on-resistance requirement.
Solution Approach 2:
The patent assigns different characteristics to different FETs in the parallel configuration. The first power FET has larger channel width for low on-resistance, while the second power FET has smaller channel width and higher on-state resistance. This local quality differentiation allows each FET to operate within its safe operating area while collectively providing the required performance.
2Reliability
If multiple power FETs are used in parallel to reduce thermal runaway risk, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-regulating mechanism where each power FET's gate is controlled by sense circuits that monitor its own drain-to-source voltage. When a FET approaches saturation, its gate drive is automatically reduced, and current is redirected to other FETs in the parallel configuration. This self-service approach provides thermal protection without requiring complex external control circuitry.
Solution Approach 2:
The patent employs feedback control through sense circuits that continuously monitor the drain-to-source voltage of each power FET. When saturation is detected, the control circuit adjusts the gate drive signals accordingly, creating a closed-loop system that automatically prevents thermal runaway while simplifying the overall control architecture.
3Reliability
If current is redirected from a saturated FET to another FET, then thermal runaway is prevented, but detection precision requirements increase
Solution Approach 1:
The patent implements preliminary protection by detecting VDS saturation conditions before thermal runaway occurs. The sense circuits continuously monitor each FET's drain-to-source voltage and proactively adjust gate drive signals when saturation is detected, preventing the harmful thermal runaway condition from developing in the first place.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents thermal runaway in the first FET by redirecting current to the second FET during saturation conditions and allows for reliable thermal protection, simplifying the detection of thermal runaway and improving the safe operating area of the linear switch circuit.
Implementation Method 1
employing a thermal sense diode aligned with the second FET to detect and prevent thermal runaway
Data Source
AI summary
A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.


