Linearization of charge-redistribution based vector matrix multiplier
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Solution Overview
Problem
Existing charge-redistribution based vector-matrix multipliers suffer from non-linear dependence of output voltage on capacitive weight values, leading to inaccurate results due to the parallel connection of capacitances in the summation charge storage component and matrix memory components.
Innovation Solution
An accumulator circuit with a linearized output device, comprising a controllable variable gain amplifier and gain controller, or a tunable summation capacitance controller, to eliminate non-linearity by adjusting the gain factor or capacitance values based on column weight sum signals, ensuring a linear dependence of the output voltage on the capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitance values of matrix memory components and summation charge storage component are connected in parallel, then charge accumulation is simplified, but non-linearity is introduced causing inaccurate computational results
Solution Approach 1:
A linearization circuit is introduced as an intermediary component between the parallel-connected capacitance network and the output node. This circuit includes a variable gain amplifier with controlled gain factor and a summation capacitance component, which together compensate for the non-linearity introduced by the parallel connection, enabling accurate computational results while maintaining the simplified charge accumulation structure.
2Measurement precision
If additional linearization circuitry is added to eliminate non-linearity, then computational accuracy is improved, but device complexity and energy consumption increase
Solution Approach 1:
The linearization function is merged with the existing charge accumulation structure by integrating the linearization circuit directly into the summation charge storage component. The variable gain amplifier and controlled capacitance are combined with the parallel-connected capacitance network to form a unified circuit that performs both charge accumulation and non-linearity compensation, avoiding the need for separate linearization stages.
Solution Approach 2:
The linearization circuit utilizes parameter changes through a variable gain amplifier whose gain factor is dynamically adjusted based on the capacitance values of the matrix memory components. By controlling the gain factor according to the actual capacitance configuration, the circuit adapts to different computational tasks and maintains accuracy without requiring complex fixed-structure linearization networks.
3Measurement precision
If variable gain amplifier with controlled gain factor is used, then non-linearity is eliminated, but energy consumption increases
Solution Approach 1:
The variable gain amplifier dynamically adjusts its gain factor based on the actual capacitance values of the matrix memory components, allowing the circuit to adapt to different computational requirements. This dynamic adjustment enables the system to maintain high accuracy while minimizing energy consumption by activating the linearization function only when and where needed, rather than using a fixed high-power linearization circuit throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved computational accuracy and energy efficiency by eliminating non-linear distortions in vector-matrix multiplication, facilitating precise results without additional circuitry.
Implementation Method 1
The matrix memory components are individually tunable in their capacitance value to represent a respective weight matrix value and electrically arranged in parallel along matrix columns, each matrix column providing respective a summation charge representing a sum of partial products of an input voltage vector with respective capacitance values of the memory components in the matrix column
Implementation Method 2
a linearized output device, which is configured to receive a column weight sum signal that is indicative of a sum of the current capacitance values of the summation charge storage component and its associated matrix memory components, and using the summation capacitance value, the stored summation charge input, and the column weight sum signal, to provide a column summation output voltage, which is linearized as a function of the capacitances of the matrix memory components associated with the summation charge storage component, by eliminating a non-linearity caused by the parallel connection of capacitances of the summation charge storage component and its associated matrix memory components
Data Source
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AI summary
In the field of programmable in-memory computing devices for performing vector-matrix multiplication, an accumulator circuit for a charge-redistribution based vector-matrix multiplier is provided. The accumulator circuit provides column summation output voltages, which are linearized as a function of the capacitances of the matrix memory components associated with the summation charge storage component of a given column, by eliminating a non-linearity caused by the parallel connection of capacitances of the summation charge storage component and its associated matrix memory components in the column.