Linearized Sampling Circuit for High-Rate ADC Linearity
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Solution Overview
Problem
Analog-to-digital converters, particularly those used in high-speed communication and signal analysis, experience linearity deterioration due to leakage currents and variations in process, temperature, and voltage, especially in time-interleaved architectures.
Innovation Solution
A sampling circuit with a linearization circuit connected to input terminals and capacitors, utilizing switches with controlled on-resistance and off-resistance to maintain linearity by equalizing voltage levels across nodes, reducing the impact of leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sampling speed is increased to achieve high sampling rate, then productivity is improved, but linearity deteriorates due to leakage currents and PVT variations
Solution Approach 1:
The linearization circuit equalizes voltage levels at different nodes by introducing compensation paths. Specifically, it creates equipotential conditions between nodes affected by leakage currents and PVT variations, ensuring that voltage differences remain consistent across process, temperature, and voltage changes, thereby maintaining linearity at high sampling rates
Solution Approach 2:
The linearization circuit implements feedback mechanisms where leakage currents and PVT variations are continuously compensated. The circuit monitors voltage deviations caused by leakage and actively adjusts compensation signals to counteract these effects, creating a feedback loop that maintains linearity even as sampling speed increases
2Productivity
If time-interleaved architecture is used to achieve high sampling rate, then productivity is improved, but linearity deteriorates due to leakage currents
Solution Approach 1:
The time-interleaved architecture divides the sampling circuit into multiple parallel channels, each handling a portion of the sampling task. The linearization circuit applies segmentation by treating leakage compensation independently for each channel while maintaining coordinated operation, allowing high sampling rates through parallel processing while preserving linearity through channel-specific compensation
Solution Approach 2:
The linearization circuit acts as an intermediary between the multiple time-interleaved channels and the output. It mediates the effects of leakage currents by introducing compensation signals that balance the contributions from different channels, ensuring that the combined output maintains linearity despite the segmented architecture
Data Source
AI summary
A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.