Liner-Protected Single Diffusion Breaks in Semiconductor Fins

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Solution Overview

Problem

The existing methods for forming diffusion breaks in fin-type field-effect transistors often result in unwanted etching of epitaxial semiconductor material due to isotropic etching, leading to inefficiencies in isolating transistors and forming effective diffusion breaks.

Innovation Solution

A method involving epitaxial growth of semiconductor material in cavities within semiconductor fins, followed by selective removal of gate structures and fin portions to create a second cavity, where a dielectric liner is formed between the source/drain regions and the cavity, preventing lateral etching during the formation of a single diffusion break.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If isotropic etching is used to remove lower portions of fins from shallow trench isolation, then fin isolation is achieved, but epitaxial semiconductor material of source/drain regions is unwantedly etched

Engineering Contradiction:
Improvediffusion break formation precisionVSAvoidepitaxial semiconductor material loss
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

A liner layer is introduced as an intermediary protective barrier between the isotropic etching process and the epitaxial semiconductor material. The liner is deposited conformally across the substrate, selectively removed from the second cavity area, and remains intact during isotropic etching to protect the source/drain regions from lateral etching while allowing the fin material to be removed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The liner is deposited and patterned in advance before the isotropic etching process. This preliminary action creates a protective mask that prevents the subsequent etching process from attacking the epitaxial semiconductor material, thereby preventing material loss before it can occur

Inventive Principle:
Principle #10Preliminary action

2Reliability

If liner is deposited before removing lower portion of fin, then source/drain region protection is achieved, but process complexity increases

Engineering Contradiction:
Improvesource/drain region protectionVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The liner deposition and removal process is segmented into distinct stages: conformal liner deposition across the entire substrate, selective removal from the second cavity area using patterned removal, and preservation during subsequent etching. This segmentation allows the complex protection mechanism to be integrated into existing process flows without requiring complete process redesign

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively isolates transistors while protecting the epitaxial semiconductor material, ensuring precise and efficient formation of a single diffusion break, enhancing the density and performance of integrated circuits.

Implementation Method 1

preventing lateral etching during the formation of a single diffusion break

Methodology Applied
Scientific EffectLateral etching prevention:

Implementation Method 2

epitaxially growing a semiconductor material in a first cavity in a semiconductor fin to form a source/drain region

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS10784342B1Single diffusion breaks formed with liner protection for source and drain regions
Publication Date: 2020.09.22 GLOBALFOUNDRIES US INC
  • US10784342B1 patent drawing
  • US10784342B1 patent drawing
  • US10784342B1 patent drawing

AI summary

Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.