Liner Oxide Layer for FinFET Gate Stress Control
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Solution Overview
Problem
In the semiconductor industry, particularly in FinFET devices, the replacement gate process faces challenges in accurately controlling deposition and patterning during gate fabrication, leading to deteriorated electrical performance due to the inadvertent etching of gate dielectric and barrier layers.
Innovation Solution
A liner layer is formed on a contact etching stop layer and below an interlayer dielectric layer in the replacement gate manufacturing process, which serves as a stress modulating, blocking, and barrier layer to enhance device electrical performance by adjusting the film stack stress and preventing moisture penetration, and is converted to a liner oxide layer through thermal annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a replacement gate process is used to form metal gate electrodes, then device performance is improved, but deposition and patterning control becomes difficult leading to deteriorated electrical performance
Solution Approach 1:
A liner layer is introduced as an intermediary between the CESL and the gate structure. This liner layer acts as a protective mediator that prevents harmful etching effects from propagating to the gate dielectric and barrier layers during patterning operations, thereby maintaining manufacturing precision while enabling replacement gate process benefits
Solution Approach 2:
The liner layer is formed in advance before the gate patterning step. This preliminary action establishes a protective barrier prior to the patterning process, preventing potential damage to underlying layers and ensuring better control over the subsequent deposition and patterning operations
2Ease of manufacture
If gate dielectric and barrier layers are inadvertently etched, then manufacturing simplicity is maintained, but electrical performance deteriorates
Solution Approach 1:
The liner layer serves as a protective intermediary that absorbs or blocks harmful etching effects, allowing the patterning process to proceed without inadvertently damaging the gate dielectric and barrier layers. This maintains process simplicity while protecting electrical performance
3Device complexity
If film stack stress is not controlled, then manufacturing complexity is reduced, but device reliability decreases due to stress mismatch
Solution Approach 1:
The liner layer is designed with specific material composition and thickness parameters that enable stress modulation. By controlling the stress state of the liner layer, the overall film stack stress is balanced, preventing stress mismatch and improving device reliability without significantly increasing manufacturing complexity
Solution Approach 2:
The liner layer provides localized stress control at the interface between the CESL and the gate structure. This local quality adjustment addresses stress mismatch issues specifically where they occur, rather than requiring complex modifications to the entire film stack
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The liner oxide layer improves film integration and adhesion, reduces stress mismatch, and minimizes current leakage, thereby enhancing the electrical performance and reliability of semiconductor devices.
Implementation Method 1
the liner layer is converted to a liner oxide layer through thermal annealing
Data Source
AI summary
Semiconductor device structures having a liner layer in an interlayer dielectric structure are provided. In one example, a semiconductor device includes an active area on a substrate, the active area comprising a source/drain region, a gate structure over the active area, the source/drain region being proximate the gate structure, a spacer feature along a sidewall of the gate structure, a contact etching stop layer on the spacer feature, a liner oxide layer on the contact etching stop layer, and an interlayer dielectric layer on the liner oxide layer, wherein the liner oxide layer has an oxygen concentration level greater than the interlayer dielectric layer.