Linerless MOL Contact via Silicidation for Low Resistance
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Solution Overview
Problem
As semiconductor devices scale to smaller dimensions, contact resistance increases, and metal liners used in contacts have higher resistivity than bulk metals, leading to increased overall device resistance, particularly affecting devices with small via sizes like 10×10 nanometer square vias.
Innovation Solution
The method involves forming semiconductor devices with source/drain contacts without a metal liner by filling the source/drain regions and vias with amorphous silicon, a metal, or a silicon-metal alloy and performing a low temperature silicidation process to create a low resistance contact without a liner on the via sidewall, using a barrier layer to prevent further silicidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal liners are used in contacts, then contact structure is formed, but contact resistance increases due to higher resistivity of metal liners compared to bulk metals
Solution Approach 1:
The patent removes the metal liner layer from the contact structure, extracting the problematic high-resistivity component. The contact is formed directly with copper filling the contact hole, eliminating the tungsten or other metal liner that previously increased contact resistance. This extraction principle directly addresses the technical contradiction by removing the harmful element (metal liner) while maintaining the beneficial copper bulk metal contact.
Solution Approach 2:
The patent introduces a dielectric liner as an intermediary layer between the copper contact and the surrounding structure. This dielectric liner prevents copper diffusion into adjacent regions while maintaining low contact resistance. The intermediary dielectric layer replaces the problematic metal liner, providing both the necessary barrier function and allowing direct copper contact for low resistance.
2Length of moving object
If via size is reduced to small dimensions (e.g., 10×10 nanometer), then device scaling is achieved, but contact resistance increases significantly
Solution Approach 1:
The patent changes the material parameter of the contact from composite (metal liner + copper) to pure copper, fundamentally altering the resistivity parameter. By using copper with its inherently low resistivity and eliminating the high-resistivity metal liner, the contact resistance parameter is optimized for small via dimensions. This parameter change enables successful scaling to 10×10 nanometer vias without the contact resistance penalty that would otherwise occur.
3Reliability
If low temperature silicidation process is used, then contact resistance is reduced, but additional process steps are required
Solution Approach 1:
The patent performs preliminary actions by depositing the dielectric liner and forming the contact hole structure before copper filling. The low temperature silicidation process is applied preliminarily to the copper material to optimize its electrical properties before final contact formation. This preliminary treatment of the copper material reduces contact resistance while the process is integrated into the existing fabrication sequence, minimizing additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, achieving low resistance via/contact to the source/drain region, resulting in improved device performance by eliminating the high resistance associated with metal liners.
Implementation Method 1
performing a silicidation process to form a source/drain contact including a silicide
Implementation Method 2
depositing a metallic layer over the first layer of silicon material
Data Source
AI summary
A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.