Multi-band Link Aggregation Buffer Controller

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional Wi-Fi data transmission protocols face challenges in handling large amounts of data packets across multiple interfaces, as existing buffering and acknowledgement mechanisms are not scalable and introduce additional overhead, leading to inefficiencies in packet ordering and increased complexity.

Innovation Solution

The implementation of a link aggregator that decouples reordering buffers and acknowledgement mechanisms, using independent scoreboard contexts and shared reordering buffers to manage data packets across multiple interfaces without increasing block acknowledgement bitmap size or adding global sequence numbers, allowing for efficient multi-band link aggregation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional buffering and acknowledgement mechanisms are used for multi-interface data transmission, then packet ordering is maintained, but overhead increases and scalability deteriorates

Engineering Contradiction:
Improvepacket orderingVSAvoidbuffering and acknowledgement mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the buffering and acknowledgement mechanisms by maintaining separate scoreboard contexts for each interface while using a shared reordering buffer. This segmentation allows independent tracking of packets per interface without requiring a monolithic complex structure, thereby maintaining packet ordering while reducing overall system complexity and improving scalability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shared reordering buffer serves multiple interfaces simultaneously, making it a universal resource that can handle packets from different interfaces. This multi-functionality eliminates the need for separate buffers per interface, reducing overhead and complexity while maintaining the ability to order packets correctly across all interfaces.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If block acknowledgement bitmap size is increased to handle multiple interfaces, then more packets can be acknowledged, but overhead increases

Engineering Contradiction:
Improvepacket acknowledgement capacityVSAvoidacknowledgement overhead
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the acknowledgement mechanism by maintaining separate scoreboard contexts for each interface, each with its own bitmap. This allows the system to acknowledge packets per interface using smaller, manageable bitmaps rather than requiring one large bitmap for all interfaces, thereby reducing overall overhead while maintaining the capacity to track multiple packets.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of increasing the size of a single-dimensional bitmap, the patent introduces a new dimension by creating multiple interface-specific scoreboard contexts. This dimensional change allows the system to scale packet acknowledgement capacity by adding interface contexts rather than expanding bitmap size, effectively reducing overhead while maintaining productivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If global sequence numbers are added to manage packets across interfaces, then packet ordering is improved, but complexity and overhead increase

Engineering Contradiction:
Improvepacket ordering across interfacesVSAvoidsequence number management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the sequence number management by maintaining separate scoreboard contexts for each interface, with each context tracking sequence numbers independently. This segmentation provides the necessary packet ordering across interfaces without requiring a single global sequence number system, thereby reducing the complexity of sequence number management while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

4Productivity

If multiple interfaces are used for data transmission, then throughput is increased, but packet loss management becomes more complex

Engineering Contradiction:
ImprovethroughputVSAvoidpacket loss management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments packet loss management by maintaining separate scoreboard contexts for each interface, allowing independent tracking and management of packet status per interface. This segmentation simplifies the management of packet loss across multiple interfaces by providing clear, interface-specific visibility into packet delivery status, thereby reducing complexity while maintaining high throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scoreboard contexts provide continuous feedback about packet transmission status for each interface, enabling the system to quickly identify and manage packet loss. This feedback mechanism operates independently for each interface, making packet loss management more straightforward despite the presence of multiple interfaces, thus maintaining productivity while reducing complexity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11800402B2Methods and apparatus to perform multi-band link aggregation in a wireless network
Publication Date: 2023.10.24 INTEL CORP
  • US11800402B2 patent drawing
  • US11800402B2 patent drawing
  • US11800402B2 patent drawing

AI summary

Methods and apparatus to perform multi-band link aggregation in a wireless network are disclosed. An example apparatus includes a buffer controller to store (A) a first set of data packets that have been received on a first interface and (B) a second set of data packets that have been received on a second interface into a buffer, the first and second sets of data packets being received from a wireless device during a same time frame; and a window determiner to control a first bitmap corresponding to the first set of data packets received on the first interface and a second bitmap corresponding to the second set of data packets received on the second interface, a first size of the first bitmap and a second size of the second bitmap being smaller than a third size of the buffer.