Link Device Routing Density in Integrated Fan-Out Packages
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing circuit density due to physical constraints in two-dimensional integrated circuits, prompting the exploration of three-dimensional ICs, but existing 3D IC formation methods are complex and inefficient.
Innovation Solution
A high-density interconnect structure for integrated fan-out packages is developed, involving a carrier substrate, adhesive layer, polymer layer, seed layer, vias, semiconductor devices, encapsulant, and link devices to create a high-density routing system that overcomes traditional limitations by using semiconductor processing methods to form link devices that connect and encapsulate semiconductor dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 3D IC formation methods are used (bonding two dies together with wire bonds), then electrical connections are established between dies, but the process becomes complex and inefficient
Solution Approach 1:
The patent extracts and eliminates the intermediate carrier substrate and wire bonding steps from the traditional 3D IC formation process. By directly bonding dies to the substrate and forming conductive vias through the substrate, the complex intermediate steps are removed, simplifying the manufacturing process while maintaining electrical connection reliability
Solution Approach 2:
The patent performs preliminary actions by pre-forming conductive vias and contact pads in the substrate before die bonding. This preliminary preparation enables direct electrical connections to be established through the substrate, eliminating the need for subsequent wire bonding operations and reducing process complexity
2Ease of manufacture
If two-dimensional integrated circuits are used, then manufacturing is simpler, but circuit density is limited by physical constraints
Solution Approach 1:
The patent transitions from two-dimensional circuit layout to three-dimensional architecture by stacking multiple semiconductor dies vertically and establishing electrical connections through the substrate. This dimensional change enables significantly higher circuit density while maintaining manufacturing simplicity through direct bonding and via formation techniques
3Quantity of substance
If more devices are integrated into one chip, then circuit density increases, but design complexity increases
Solution Approach 1:
The patent segments the integrated circuit into multiple separate semiconductor dies that are bonded to a common substrate. Each die can be designed and manufactured independently with optimized functionality, reducing individual design complexity while achieving high overall circuit density through the multi-die configuration
Data Source
AI summary
A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.