Link ECC Memory Write Path With Parallel Data Masking
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Solution Overview
Problem
As memory device capacity increases, fabricating memory devices without defective memory cells becomes challenging, and existing methods for error correction and data transmission accuracy in semiconductor memory systems lead to increased write latency due to sequential performance of error correction and data masking operations.
Innovation Solution
A memory device incorporating a syndrome calculator, error corrector, and data mask (DM) calculation circuit that generates error location signals and DM signals to correct errors and mask data bits in parallel, reducing write latency by performing error correction and DM calculation simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction and data masking operations are performed sequentially, then each operation can be completed accurately, but write latency increases
Solution Approach 1:
The patent merges the error correction operation and data masking operation into a single unified process. The syndrome calculator, error corrector, and DM calculation circuit operate simultaneously on the received data, combining two previously sequential operations into one parallel process, thereby reducing write latency while maintaining data accuracy.
Solution Approach 2:
The DM calculation circuit performs preliminary calculation of the data mask signal based on the received data and error location signal before the error correction is fully completed. This preliminary action allows the masking operation to be prepared in advance and executed concurrently with error correction, reducing the overall write latency.
2Quantity of substance
If memory device capacity increases, then storage capability improves, but fabrication of defect-free memory cells becomes difficult
Solution Approach 1:
The system performs preliminary error detection and location during the write operation before data is fully stored. By calculating the syndrome and identifying error locations in advance, the system can correct errors proactively, compensating for the increased likelihood of defects in high-capacity memory devices.
Solution Approach 2:
The syndrome calculator provides feedback about potential errors in the received data, and the error location signal provides feedback about specific bit positions that contain errors. This feedback mechanism allows the system to identify and correct defects, enabling high-capacity memory devices to maintain data integrity despite manufacturing challenges.
Data Source
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AI summary
A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.