Link Partner Error Reporting Through FEC Counter Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional error correction methods in high-speed communication networks, such as those operating at 10 Gb/s or greater, experience higher error rates and fail to provide effective error reporting between link partners, leading to network performance degradation due to false positives and negatives.
Innovation Solution
Implementing error correction processes that include forward error correction (FEC) with enhanced error reporting mechanisms, where error correction information is tracked using counters and reported through alignment markers, allowing link partners to monitor and manage network health efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward error correction (FEC) is implemented for high-speed networks, then error correction capability is improved, but error reporting accuracy deteriorates due to false positives and negatives
Solution Approach 1:
The error correction information is divided into multiple separate counters (e.g., C1-C15 for different error types, C16 for uncorrectable errors). Each counter tracks specific error conditions independently, allowing precise reporting without false positives or negatives. This segmentation enables accurate error classification while maintaining FEC correction capabilities.
Solution Approach 2:
The patent implements feedback mechanisms where error counters are reported back to the transmitting end through alignment markers. This feedback loop allows the transmitting end to adjust transmission parameters based on actual error conditions, improving reporting accuracy while maintaining error correction effectiveness. The feedback includes detailed error type information rather than just overall error counts.
2Device complexity
If conventional error correction processes are used, then implementation simplicity is improved, but error reporting capability deteriorates due to insufficient reporting among link partners
Solution Approach 1:
The error counter reporting mechanism is integrated into the existing alignment marker structure used for synchronization. This allows the same communication infrastructure to serve dual purposes: maintaining synchronization and reporting detailed error information. The alignment markers carry both timing information and error counter data, eliminating the need for separate reporting channels.
Solution Approach 2:
Alignment markers serve as intermediaries that carry error counter information between link partners. These markers are already present in the data stream for synchronization purposes, and they now additionally transport error reporting data. This intermediary approach enables comprehensive error reporting without adding separate communication overhead.
3Measurement precision
If error counters are tracked for each data unit, then error detection precision is improved, but processing complexity increases
Solution Approach 1:
Error counters are initialized and ready to track errors before data transmission begins. The counting mechanism is pre-configured to monitor specific error types (correctable errors C1-C15, uncorrectable errors C16). This preliminary setup allows immediate and precise error detection without requiring complex real-time analysis during data processing.
Solution Approach 2:
The patent uses distinct parameter values (counter identifiers C1-C16) to represent different error types. Each counter tracks a specific error condition with its own increment rule, making the tracking system systematic and manageable. This parameterization approach simplifies processing by providing clear, discrete categories for error classification rather than requiring continuous analysis.
Data Source
AI summary
Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.