Link Interface Unit Clock Domain Crossing Bandwidth
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Solution Overview
Problem
In systems on chips (SoCs) with agents operating at different clock frequencies, clock domain crossings introduce bubbles, leading to increased latency and reduced bandwidth utilization in bus fabric links.
Innovation Solution
Implementing link interface units (LIUs) that manage transactions by holding up the last data beat of a transaction until the command of a subsequent transaction is ready, allowing simultaneous transmission of the last data beat and the command, thereby optimizing bandwidth utilization across clock frequency mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred between agents with different clock frequencies using conventional sequential transmission, then clock domain crossing is achieved, but bubbles are introduced causing increased latency and reduced bandwidth utilization
Solution Approach 1:
The patent implements continuous transmission by allowing the last data beat of a first transaction and the command of a second transaction to be sent simultaneously on the same clock cycle. This eliminates idle bubbles between transactions and maintains continuous useful action on the link, thereby improving bandwidth utilization while maintaining reliable clock domain crossing.
Solution Approach 2:
The transmit unit determines in advance whether the second transaction's command is ready before sending the last data beat of the first transaction. This preliminary check allows the system to prepare for simultaneous transmission, ensuring that the last data beat can be held up appropriately without introducing bubbles, thus maintaining continuous data flow.
2Productivity
If the last data beat is held up until the command is ready, then simultaneous transmission is achieved improving bandwidth, but transmission timing becomes more complex
Solution Approach 1:
The transmit unit uses feedback signals to determine whether the second transaction's command is ready before sending the last data beat of the first transaction. This feedback mechanism allows the system to dynamically adjust timing based on actual transaction readiness, enabling simultaneous transmission while maintaining manageable control logic through structured signal exchange.
Data Source
AI summary
Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.