Link Layer Register Persistent Error Storage

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Solution Overview

Problem

Hardware controllers face challenges in error recovery due to the overwrite of error information, making it difficult to assess and correct errors, which can lead to downtime and increased costs, as the conditions under which the error occurred need to be replicated to determine the cause.

Innovation Solution

A hardware controller is configured with a link layer register that persistently stores errors, allowing a processor to address them after they have been overwritten, enabling the differentiation between critical and noncritical errors and pausing I/O requests until critical errors are corrected.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If error information is stored in the link layer, then error detection capability is improved, but error information is overwritten when another error is detected, leading to loss of diagnostic data

Engineering Contradiction:
Improveerror informationVSAvoiderror recovery capability
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The patent creates a copy of the error information from the link layer error register to a persistent storage location (system management controller or non-volatile memory). This copy mechanism ensures that even when the original error information is overwritten in the link layer, a preserved copy remains available for diagnostic purposes, thereby preventing information loss while maintaining reliable error recovery capability

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces an intermediary component (system management controller or error logging mechanism) that acts as a mediator between the link layer error register and persistent storage. This intermediary captures and stores error information, preventing its loss when overwritten, while allowing the link layer to continue functioning with its overwrite behavior, thus resolving the contradiction between information preservation and system reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If error information is persistently stored, then error recovery is simplified, but storage footprint on the hardware controller increases

Engineering Contradiction:
Improveerror recovery processVSAvoidstorage footprint
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent extracts the persistent error storage function from the link layer hardware and relocates it to a separate system management controller or external non-volatile memory. This extraction allows the link layer to maintain its compact form factor while error information is preserved externally, simplifying error recovery without significantly increasing the storage footprint of the hardware controller itself

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent moves error storage from the horizontal dimension (link layer register within the controller) to a vertical dimension (external system management controller or non-volatile memory). This dimensional transition enables persistent error storage while maintaining the hardware controller's compact footprint, as the storage resource is utilized in a different architectural layer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If the hardware controller monitors errors continuously, then error detection capability is improved, but downtime increases when errors need to be replicated for analysis

Engineering Contradiction:
Improveerror detection capabilityVSAvoidcontroller downtime
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements preliminary action by continuously capturing and persistently storing error information as it occurs, rather than waiting for errors to be replicated for analysis. The error information is preserved in real-time in the link layer register and copied to persistent storage, so when errors need to be analyzed, the data is already available, eliminating the need for time-consuming condition replication and reducing controller downtime

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8589722B2Methods and structure for storing errors for error recovery in a hardware controller
Publication Date: 2013.11.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8589722B2 patent drawing
  • US8589722B2 patent drawing
  • US8589722B2 patent drawing

AI summary

Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.