Link Stack Prefetch Augmentation for Pipeline Cache Misses

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Solution Overview

Problem

Sequential prefetchers in pipeline architectures struggle to accurately predict large jumps in code, leading to cache misses that stall processors, whereas non-sequential prefetchers can capture such jumps but have a larger physical footprint and complex algorithms.

Innovation Solution

A link stack based prefetch augmentation method that uses sequential prefetching to predict and prefetch instructions, leveraging call graph information to anticipate non-sequential addresses and store them in cache memory, reducing cache misses and processor stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential prefetching is used to predict and prefetch instructions, then processor performance is improved and cache misses are reduced, but the ability to accurately predict large jumps in code is limited

Engineering Contradiction:

Improveprocessor performanceVSAvoidprediction accuracy for large jumps

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent segments the prefetching mechanism into two distinct components: a sequential prefetcher that handles sequential instruction streams and a link stack-based component that handles non-sequential jumps. This segmentation allows each component to specialize in its strength while working together to solve the overall prediction problem.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The link stack serves as an intermediary structure that bridges sequential prefetching and non-sequential jump handling. It stores return addresses and enables the system to anticipate and prefetch instructions at jump targets without requiring a full non-sequential prefetcher.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If non-sequential prefetching is used to capture large jumps in code, then prediction accuracy is improved, but physical footprint and algorithm complexity increase

Engineering Contradiction:

Improveprediction accuracy for large jumpsVSAvoidphysical footprint and algorithm complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts only the essential functionality needed for non-sequential prefetching (handling function calls and returns) and implements it through the link stack mechanism. This avoids the need for a complete non-sequential prefetcher while still capturing the most important non-sequential patterns.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The link stack, originally designed for function call management, is given the additional function of enabling non-sequential prefetching. This multi-functionality eliminates the need for separate dedicated structures for both purposes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If non-sequential prefetching is used to predict large jumps, then cache misses are reduced, but processing overhead increases

Engineering Contradiction:

Improvecache hit rateVSAvoidprocessing overhead

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Instead of implementing full non-sequential prefetching, the patent applies partial action by using only the link stack information that is already being maintained for function call management. This provides some non-sequential prefetching capability without the complete overhead of a dedicated non-sequential prefetcher.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11586440B2Link stack based instruction prefetch augmentation

Publication Date: 2023.02.21 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A computer-implemented method of performing a link stack based prefetch augmentation using a sequential prefetching includes observing a call instruction in a program being executed, and pushing a return address onto a link stack for processing the next instruction. A stream of instructions is prefetched starting from a cached line address of the next instruction and is stored in an instruction cache.