Link Status Detection via Clock Lane Pattern
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Solution Overview
Problem
Existing communication systems face challenges in reliably detecting link status between chips with different software stacks, leading to initialization failures due to channel noise and the need for additional hardware resources.
Innovation Solution
A method using a dynamic pattern transmitted via the clock lane of the link at a slow clock speed to determine link readiness, allowing each device to initialize receivers and transmitters and detect incoming patterns without additional hardware or software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-managed initialization is used to detect link status, then communication between chips with different software stacks can be achieved, but reliability deteriorates due to unsynchronized initialization sequences and channel noise
Solution Approach 1:
The patent introduces a dedicated hardware circuit that acts as an intermediary to detect link status independently of software stacks. This hardware intermediary monitors the communication channel directly and generates interrupt signals when link status changes occur, eliminating the need for software to poll or negotiate link status, thus resolving the contradiction between software compatibility and detection reliability
Solution Approach 2:
The patent replaces the software-based link status detection mechanism with a hardware-based electrical detection system. The hardware circuit continuously monitors voltage levels and signal presence on the communication channel, using electrical fields rather than software protocols to detect link status, thereby achieving reliable detection independent of software stack variations
2Reliability
If additional hardware is used to communicate link status, then detection reliability is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent designs the hardware detection circuit to perform multiple functions: it detects link status, generates interrupt signals, and can work with existing communication protocols. By making the hardware circuit universal and multi-functional, the patent avoids adding dedicated separate components for each function, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The patent merges the link status detection function with the existing communication interface hardware. The detection circuit is integrated into the same hardware block that handles data transmission, sharing common components such as signal lines and processing units. This merging approach allows reliable link status detection to be achieved without adding significant hardware overhead
Data Source
AI summary
A system includes a first device and a second device coupled to a link having one or more paths associated with transmitting a clock signal. The first device is to transmit a set of bits associated with a pattern via the one more paths. The set of bits are transmitted using a first clock signal having a first frequency less than a second frequency associated with data transmission operations. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits over a first period, and determine the number of pulses, associated with the set of bits, satisfies a predetermined condition relating to the number of pulses for the first period. The second device is to initiate a training of the link in response to determining the number of pulses satisfies the predetermined condition.