Link Training Clock Adjustment for Asynchronous Timing Margin Loss

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional solutions for asynchronous clock timing issues in high-speed data transmission, such as DDR and eMMC, are ineffective in compensating for timing losses due to non-linearity in physical transmission media, leading to unreliable data read operations, especially when the host device lacks a dedicated phase-locked loop or de-skew circuit.

Innovation Solution

The implementation of link training logic between the host device and the device, which includes a duty cycle monitor and adjustor, allows for the detection and correction of duty cycle distortion in the strobe signal, adjusting the forward clock signal to maintain timing accuracy without relying on filtering mechanisms like PLL or de-skew circuits, thereby ensuring reliable data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional duty cycle correction techniques are used at the host device, then host-to-device timing loss is filtered to some extent, but device-to-host timing losses cannot be compensated

Engineering Contradiction:

Improvetiming loss compensationVSAvoidbidirectional timing compensation

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent inverts the conventional approach by implementing duty cycle correction at the device end rather than the host end. The device monitors its own transmitted strobe signal's duty cycle and generates correction signals to adjust its output clock signal, enabling the device to compensate for timing losses in the device-to-host direction that conventional host-side corrections cannot address.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The device performs self-correction of its clock signal by monitoring its own transmitted strobe signal characteristics. The duty cycle monitor at the device end detects duty cycle distortion in the strobe signal and automatically generates control signals to adjust the clock signal, enabling the device to self-correct timing issues without requiring complex host-side intervention for bidirectional compensation.

Inventive Principle:

Principle #25Self-service

2Reliability

If digital techniques are used at the host device to correct duty cycle, then correction can be implemented, but the solution is not robust against process variation and noise

Engineering Contradiction:

Improvecorrection robustnessVSAvoidprocess variation and noise sensitivity

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent replaces fragile digital correction techniques with an analog duty cycle correction mechanism. The analog circuit directly adjusts the clock signal's duty cycle based on feedback from the duty cycle monitor, providing continuous and smooth correction that is less sensitive to process variation and noise compared to discrete digital correction methods.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements a feedback mechanism where the duty cycle monitor continuously monitors the strobe signal's duty cycle and feeds this information back to the duty cycle corrector. This closed-loop feedback enables real-time adjustment of the clock signal to maintain optimal duty cycle despite process variation and noise, significantly improving correction robustness.

Inventive Principle:

Principle #23Feedback

3Ease of operation

If the device uses a received forwarded clock signal from the host device, then the device can perform data transactions, but serious system asynchronous clock timing issues occur

Engineering Contradiction:

Improvedevice data transaction capabilityVSAvoidasynchronous clock timing

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary correction to the clock signal before it is used for data transactions. The duty cycle corrector adjusts the clock signal's duty cycle in advance based on feedback from the duty cycle monitor, ensuring that the clock signal has optimal timing characteristics before being used for device operations, thereby preventing timing issues before they occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the duty cycle parameter of the clock signal to compensate for timing losses. By dynamically adjusting the duty cycle parameter based on monitored strobe signal characteristics, the system maintains optimal timing margins for data transactions despite asynchronous clock issues, improving reliability without sacrificing operational capability.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9742603B1Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces

Publication Date: 2017.08.22 INTEL CORP

AI summary

In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal.