Multi-Layer Link Wiring Layout for Narrow-Bezel Flicker Control

The patent applies dimensional change by transitioning from a single-layer wiring structure to a multi-layer wiring structure. Specifically, different link wirings are disposed in different layers (first link wiring in a first layer, second link wiring in a second layer), allowing multiple signal paths to coexist in a limited bezel area without lateral expansion, thus resolving the contradiction between high resolution requirements and bezel area constraints.

The patent separates adjacent link wirings into different layers to eliminate parallel proximity in the same layer, which is the source of electric field generation. By stacking wirings vertically rather than placing them side-by-side horizontally, the design maintains VRR operation capability while preventing electric field interference that causes flicker.

The patent resolves the contradiction by utilizing the vertical dimension through multi-layer construction. Adjacent link wirings that would otherwise be forced into close lateral proximity (causing electric field interference) are instead separated vertically across different layers, enabling narrow bezel design without sacrificing electrical isolation between signal paths.

While multi-layer structures are inherently more complex than single-layer structures, the patent implements layering in a manner that leverages existing semiconductor manufacturing capabilities. The first and second link wirings in different layers can be formed using standard multi-layer PCB or thin-film fabrication processes, achieving flicker elimination through vertical separation while maintaining reasonable manufacturing feasibility.