Linked Bank Refresh for Memory Bus Bandwidth Recovery
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining information integrity due to memory cell discharge over time, requiring frequent refresh operations that occupy the command and address bus, limiting bandwidth availability for access operations.
Innovation Solution
Implementing linked bank refresh operations, where access commands include the option for simultaneous refresh operations in linked banks, allowing more flexible use of the command and address bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently to maintain information integrity, then memory reliability is improved, but command and address bus availability for access operations deteriorates
Solution Approach 1:
The memory system is divided into multiple independent banks that can operate simultaneously. Refresh operations on one bank do not block access operations on other banks, as each bank has its own dedicated command and address bus interface. This segmentation allows parallel execution of refresh and access operations across different banks.
Solution Approach 2:
The patent introduces a bank dimension to the memory architecture, transforming the single-bus sequential operation into a multi-bank parallel operation. By adding the bank address dimension to the command structure, the system can independently manage refresh and access operations across multiple banks simultaneously, effectively utilizing the fourth dimension of parallelism.
2Reliability
If refresh operations occupy the command and address bus, then memory cell charge restoration is ensured, but access operation speed deteriorates
Solution Approach 1:
The memory system is divided into multiple independent banks that can operate simultaneously. Refresh operations on one bank do not block access operations on other banks, as each bank has its own dedicated command and address bus interface. This segmentation allows parallel execution of refresh and access operations across different banks.
Solution Approach 2:
The system ensures continuous refresh operations across all banks by distributing refresh commands across multiple banks in parallel. While one bank is being refreshed, other banks can simultaneously perform access operations, ensuring that refresh operations continue without interruption while maintaining high access speeds.
3Reliability
If per-bank refresh commands are issued to maintain memory integrity, then information preservation is improved, but command bus utilization efficiency deteriorates
Solution Approach 1:
The patent merges refresh operations with access operations by allowing access commands to trigger automatic refresh operations in linked banks. When an access command is issued to one bank, the system automatically performs a refresh operation in a linked bank without requiring a separate refresh command, thereby combining two operations into one bus transaction.
Solution Approach 2:
The system performs refresh operations in advance by automatically triggering them during access operations on linked banks. This preliminary action ensures that memory cells are refreshed before they are needed, maintaining memory integrity without requiring dedicated bus time for refresh operations.
Data Source
AI summary
A memory device includes a plurality of memory banks. The memory device receives a linked activation command along with a bank address which specifies a first one of the memory banks. While an access operation is performed on the first memory bank responsive to the linked activation command, a refresh operation is performed on a second memory bank responsive to the linked activation. The first and the second memory banks are part of a bank link group. A second linked activation command may be received a time after first linked activation command which is less than a refresh delay tRFCL as long as the second linked activation command is to a different bank link group.