Linked DMA Descriptors for Low-Latency Memory Transfers
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Solution Overview
Problem
Conventional processing accelerators, such as vector processing units, face inefficiencies due to system latencies in memory access and inefficient configuration techniques, particularly in robotic systems like automated vehicles, limiting the scalability and efficiency of image and video processing.
Innovation Solution
Implementing a pixel processing engine with a 2D array of processing engines that can process data independently of a common memory source and adjust bit width, using DMA descriptors to manage memory access and dynamically update data transfers based on frame content, reducing latency and improving math-to-memory ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional accelerators use a common memory source for data processing, then data access is simplified, but system latencies increase due to memory reading and writing operations
Solution Approach 1:
The patent divides the processing system into multiple processing engines (PEs) arranged in a two-dimensional array, where each PE can independently access memory. This segmentation eliminates the single memory access bottleneck by distributing memory access across multiple PEs, thereby reducing system latencies while maintaining simplified access configuration.
Solution Approach 2:
The patent transitions from a conventional one-dimensional or scalar processing architecture to a two-dimensional array of processing engines. This dimensional change enables parallel memory access from multiple PEs simultaneously, reducing the time penalty associated with memory operations while keeping the access mechanism relatively simple.
2Ease of manufacture
If conventional DMA systems use fixed configuration techniques, then implementation is simpler, but efficiency decreases due to inability to adapt to varying data requirements
Solution Approach 1:
The patent implements dynamic DMA descriptors that can be updated and modified during runtime based on actual data transfer requirements. Instead of fixed configuration, the system allows descriptors to adapt to varying frame sizes, data formats, and transfer patterns, significantly improving data transfer efficiency while maintaining relatively simple implementation through standardized descriptor structures.
Solution Approach 2:
The patent enables modification of DMA descriptor parameters such as source/destination addresses, transfer sizes, and data formats during operation. This parameter flexibility allows the DMA system to efficiently handle diverse data processing tasks without requiring complex reconfiguration, balancing ease of implementation with high productivity.
3Device complexity
If pixel processing engines are constrained by fixed bit width, then hardware design is simpler, but scalability and processing capability are limited
Solution Approach 1:
The patent implements processing engines with dynamically adjustable bit width capabilities. Each PE can be configured to operate at different bit widths (e.g., 8-bit, 16-bit, 32-bit) based on the specific processing task requirements. This dynamic configurability enhances scalability and versatility while maintaining relatively simple hardware design through parameter-based adaptation rather than multiple fixed architectures.
Solution Approach 2:
The patent designs processing engines that can universally handle multiple data types and bit widths within the same hardware structure. This multi-functionality allows a single PE design to adapt to various processing requirements (image processing, video processing, different data formats) without requiring separate specialized hardware, thus achieving scalability with controlled complexity.
4Device complexity
If conventional systems use centralized memory access for all processing operations, then memory management is simpler, but bottlenecks increase reducing overall system throughput
Solution Approach 1:
The patent segments the memory access function by providing each processing engine with independent memory access capabilities. Instead of a single centralized memory interface, multiple PEs can simultaneously access memory through their own interfaces, eliminating the bottleneck effect and increasing system throughput while maintaining relatively simple memory management through standardized access protocols.
Solution Approach 2:
The patent introduces DMA controllers as intermediary components that manage memory access for multiple PEs. These intermediaries handle the complexity of memory management, address translation, and data buffering, allowing PEs to focus on processing while the DMA system manages memory operations efficiently, thus increasing throughput without significantly increasing overall system complexity.
Data Source
AI summary
In various examples, systems and methods are disclosed that relate to linking and performing direct memory access (DMA) transfers. In one example, an accelerator can generate data associated with a descriptor that represents multiple DMA transfers associated with a plurality of DMA transfer types. The accelerator can provide the data associated with the descriptor to a device (or group of devices) involved in performing the DMA transfers as a set of linked DMA transfers. In response to receiving the data associated with the descriptor, the device(s) that receive the data associated with the descriptor can be configured to perform DMA transfers and allow for movement of the data specified by the descriptor to be moved from source memory to destination memory.