Memory Circuit LIO Switching for Area Reduction
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices changes, affecting operating voltages and overall IC performance.
Innovation Solution
A memory circuit design that includes a set of memory cells, bit lines, and a local input output (LIO) circuit, where the LIO circuit incorporates a switching circuit and a latch circuit that functions as both a sense amplifier and a write-in latch, reducing the number of transistors and logic devices required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate sense amplifier and write-in latch circuits are used, then the functionality is complete and reliable, but the area occupation and power consumption increase
Solution Approach 1:
The patent combines the sense amplifier and write-in latch circuits into a single integrated circuit block. The latch circuit is designed to perform both sensing and write-in functions by utilizing the same circuit elements (transistors, bit lines, and storage nodes) for both operations, thereby reducing the total area occupation while maintaining the functionality of separate circuits.
Solution Approach 2:
The latch circuit is designed with multi-functionality to serve as both a sense amplifier during read operations and a write-in latch during write operations. The same circuit structure handles both functions by switching its operation mode based on control signals, eliminating the need for separate dedicated circuits and reducing overall area consumption.
2Reliability
If separate sense amplifier and write-in latch circuits are used, then the functionality is complete and reliable, but the power consumption increases
Solution Approach 1:
The patent combines the sense amplifier and write-in latch circuits into a single integrated circuit block. The latch circuit is designed to perform both sensing and write-in functions by utilizing the same circuit elements (transistors, bit lines, and storage nodes) for both operations, thereby reducing the total area occupation while maintaining the functionality of separate circuits.
Solution Approach 2:
The latch circuit is designed with multi-functionality to serve as both a sense amplifier during read operations and a write-in latch during write operations. The same circuit structure handles both functions by switching its operation mode based on control signals, eliminating the need for separate dedicated circuits and reducing overall area consumption.
3Area of stationary object
If the IC size is reduced, then the device becomes more compact, but the resistance of conductive lines changes affecting operating voltages
Solution Approach 1:
The patent addresses the voltage variation issue by adjusting circuit parameters such as transistor sizing, threshold voltages, and operating points to compensate for the increased line resistance in smaller ICs. The latch circuit is designed with optimized transistor dimensions and threshold voltages to ensure stable operation despite changes in conductive line resistance.
Data Source
AI summary
A memory circuit includes a first and second bit line coupled to a set of memory cells, a local input output (LIO) circuit coupled to the set of memory cells by the first and second bit line. The LIO circuit includes a first and second data line, and a first control circuit. The LIO circuit further includes a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation of the set of memory cells, and to electrically isolate the first and second data line from the first and second input signal during a read operation of the set of memory cells. The LIO circuit further includes a first latch circuit configured as a sense amplifier during the read operation, and configured as a write-in latch during the write operation.