Liquid Metal Shielding Frame for Fine-Pitch Interconnect EMI
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Solution Overview
Problem
Signal integrity performance degradation due to electromagnetic interference (EMI) and crosstalk coupling at tightly coupled first level interconnects (FLI) between a silicon die and a package substrate, particularly at bump pitch geometries ≤110 μm, limits I/O data-rate and silicon area scaling, and existing solutions like reduced Signal:Ground ratio, ground-webbing designs, and receiver device circuitry equalization come with drawbacks such as increased silicon footprint, power consumption, and incomplete shielding.
Innovation Solution
The use of a dielectric frame with a conductive layer, including a liquid metal alloy, to provide continuous electrical shielding and improved vertical crosstalk shielding at C4 interconnects, allowing for reduced bump pitch and relaxed Signal-to-Ground ratio, while enhancing power delivery and package warpage control through increased Vcc bump contact area and volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If reduced Signal:Ground ratio is implemented to improve EMI shielding, then electromagnetic interference shielding is improved, but silicon footprint increases
Solution Approach 1:
The patent introduces a vertical shielding dimension by placing a conductive layer within the frame structure between the silicon die and package substrate, rather than relying solely on planar Signal:Ground ratio adjustment. This third-dimensional approach provides EMI shielding without increasing the horizontal silicon footprint.
Solution Approach 2:
The conductive layer acts as an intermediary shielding element between the signal bumps and ground plane, providing EMI protection through a intermediate conductive barrier that does not require changing the Signal:Ground ratio at the bump level.
2Object-affected harmful factors
If ground-webbing design is implemented to improve EMI shielding, then electromagnetic coupling is reduced, but routing density is limited at confined bump break-out area
Solution Approach 1:
The conductive layer provides shielding in the vertical dimension between die and substrate, eliminating the need for complex ground-webbing routing in the confined bump break-out area. This resolves the routing density limitation while maintaining EMI shielding effectiveness.
3Reliability
If receiver device circuitry equalization is implemented to improve signal integrity, then signal integrity performance is improved, but power consumption increases
Solution Approach 1:
The patent converts the harmful electromagnetic coupling into a controlled shielding arrangement using the conductive layer, improving signal integrity through passive physical shielding rather than active circuitry equalization, thereby reducing power consumption.
4Productivity
If bump pitch is reduced to improve I/O density, then I/O density increases, but electromagnetic coupling between adjacent bumps increases
Solution Approach 1:
The conductive layer serves as an intermediary shielding barrier between closely-spaced bumps, enabling reduced bump pitch while maintaining low electromagnetic coupling through the intermediate conductive shield.
Solution Approach 2:
By adding vertical shielding through the conductive layer, the patent enables tighter horizontal bump spacing without increasing electromagnetic coupling, thus achieving higher I/O density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces silicon footprint, improves data bandwidth, and power integrity, while maintaining signal integrity and controlling package warpage, thus enabling miniaturization and higher I/O density without the drawbacks of existing solutions.
Implementation Method 1
a conductive layer, including a liquid metal alloy, to provide continuous electrical shielding and improved vertical crosstalk shielding
Data Source
AI summary
The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.