List Structure Control Circuit for High-Speed Data Insertion
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Solution Overview
Problem
Existing list structure control methods, whether software-based or hardware-implemented, face inefficiencies in data insertion and removal operations due to the need for tracing through the list structure, leading to high processing times and increased latency, especially as the number of components grows.
Innovation Solution
A hardware-implemented list structure control circuit that uses a combination of memory devices and update control circuits with selection signals to manage data insertion and removal operations, allowing for parallel processing and minimizing circuit latency through the use of Adders or Carry Save Adders, enabling high-speed data retention and update operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a list structure is used for data management, then insertion and removal operations can be performed efficiently, but search operations require tracing through N-1 components from the top, resulting in increased processing time
Solution Approach 1:
The patent introduces a hierarchical dimension to the traditional linear list structure by organizing data into groups with group headers. Each group header contains a pointer to the first component of its group, creating a two-level navigation system. This dimensional change allows search operations to first locate the appropriate group (reducing the search space from N components to N/G groups) and then search within that group, thereby resolving the contradiction between efficient insertion/removal and fast search.
2Speed
If an array structure is used for data management, then random access to each component can be achieved with one-time reference, but insertion and removal operations require copying all posterior data components, resulting in processing time proportional to the number of components
Solution Approach 1:
The patent segments the array structure into multiple groups, where each group is managed independently with its own header. This segmentation allows insertion and removal operations to be confined to specific groups rather than requiring copying of all posterior data across the entire array. The group header structure enables efficient pointer-based reorganization within groups, resolving the contradiction between fast random access and efficient insertion/removal operations.
3Adaptability or versatility
If a traditional link list method is used, then data structures can be dynamically managed, but a large number of structures must be rewritten during insertion and removal operations, resulting in long processing cycles
Solution Approach 1:
The patent merges the advantages of array structures (contiguous memory layout, fast access) with link list structures (dynamic insertion/deletion) by creating a hybrid hierarchical structure. Group headers are stored contiguously like arrays, while components within groups maintain pointer-based linking for dynamic management. This merging reduces the number of structures that need to be rewritten during operations, as changes are localized to specific groups rather than requiring updates across the entire data structure, thereby resolving the contradiction between adaptability and processing speed.
Data Source
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AI summary
A list structure control circuit includes memories each individually stores data, selection circuits arranged for each of the memories and series-connect the memories so that data stored in each memory has an order relation, and an update control circuit that adds a position selection signal which specifies a position for data insertion or data removal to a fixed value, or subtracts the position selection signal from the fixed value, generates an enable signal based on the calculation result, and controls data retention performed in the memories or data update performed in the memories using data of a memory in precedent stages based on the generated enable signal, wherein the selection circuits are controlled based on the position selection signal at the time of the data insertion, and data stored in a memory located at the position specified by the position specification signal is updated with data to be inserted.