List Decode Circuits for Low-Latency Reed-Solomon Error Correction
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Solution Overview
Problem
Reed-Solomon codes struggle to correct a large number of symbol errors, particularly when error patterns exceed half the code distance, as they typically only correct up to half the code distance, limiting their effectiveness in high bit-error-rate scenarios without increasing memory overhead or altering encoding.
Innovation Solution
The implementation of a parallelized and pipelined list decode method for Reed-Solomon codes, utilizing a device with polynomial evaluation, field division, discrepancy filter, and enhanced error locator polynomial circuits, which generates speculative discrepancy values and filters them to enhance error correction capability up to half the code distance, allowing for correction of additional symbol errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon codes are used with standard error correction methods, then the code can correct up to half the code distance symbol errors, but it cannot correct a larger number of symbol errors (τ≥D/2) without increasing memory overhead or altering encoding
Solution Approach 1:
The patent segments the error correction process into multiple independent circuits: polynomial evaluation circuits, field division circuits, discrepancy filter circuits, and error locator polynomial circuits. Each circuit handles a specific portion of the list decoding process, allowing parallel processing of multiple potential error patterns simultaneously. This segmentation enables correction of τ≥D/2 errors without requiring increased memory overhead by distributing the computational load across specialized hardware modules.
Solution Approach 2:
The patent transitions from sequential error correction to parallel processing by implementing a list decoding approach that evaluates multiple potential error patterns simultaneously across different computational dimensions. The parallelized and pipelined architecture processes multiple discrepancy values and error locator polynomials in concurrent streams, effectively adding a temporal parallelism dimension that enables higher error correction capability without proportionally increasing memory resources.
2Reliability
If standard Reed-Solomon decoding is used, then the decoding process is simpler, but it cannot handle high bit-error-rate scenarios effectively
Solution Approach 1:
The patent implements preliminary action by pre-computing and storing polynomial evaluation results in lookup tables before the actual decoding process. The polynomial evaluation circuits pre-calculate values for all possible error patterns, and these results are stored for rapid retrieval during discrepancy calculation. This preliminary preparation enables the decoder to quickly evaluate multiple potential error patterns under high bit-error-rate scenarios without performing computationally intensive calculations in real-time, thereby handling high error rates effectively while managing circuit complexity through optimized pre-computation.
Solution Approach 2:
The patent introduces intermediary circuits that facilitate the complex list decoding process. The discrepancy filter circuit acts as an intermediary that selectively passes only those discrepancy values that correspond to valid error patterns, filtering out invalid candidates before they reach the error locator polynomial circuits. This intermediary filtering mechanism simplifies the overall decoding process by reducing the search space, allowing the system to handle high error rates effectively while maintaining manageable circuit complexity through staged processing.
3Reliability
If list decoding methods are implemented to correct more errors, then more symbol errors can be corrected, but the processing time and latency increase
Solution Approach 1:
The patent implements continuous useful action through a pipelined architecture where multiple stages of the list decoding process operate concurrently and continuously. The pipeline consists of overlapping stages: polynomial evaluation, field division, discrepancy calculation, filtering, and error locator polynomial generation. While one set of data is being processed in early stages, another set is being processed in later stages, ensuring that the decoder continuously produces corrected output without idle cycles. This continuous pipelined operation enables correction of τ≥D/2 errors while maintaining low latency by eliminating processing gaps between stages.
Solution Approach 2:
The patent employs periodic action through iterative refinement of the list decoding process. The discrepancy filter circuits periodically update and refine the list of potential error patterns based on calculated discrepancies, and the error locator polynomial circuits periodically generate updated error locators. This periodic refinement occurs in synchronized cycles that allow the system to converge on the correct error pattern efficiently, balancing thorough error correction with time constraints by using structured iterative updates rather than exhaustive continuous search.
Data Source
AI summary
Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.