Lithographic Model Defect Rate Prediction

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Solution Overview

Problem

Current methods for predicting defect rates in integrated circuit (IC) manufacturing are inaccurate and labor-intensive, leading to poor yield and increased costs due to stochastic defects like pinching and bridging during lithography.

Innovation Solution

A calibrated lithographic model is used to generate output based on IC design layouts, extracting chemical parameters such as inhibitor concentration, which is then used in a defect rate model to predict defect rates, employing functions like complementary error functions, quadratic, or cubic models for accurate and rapid defect prediction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional defect rate prediction methods are used, then labor-intensive manual analysis can be performed, but prediction accuracy is poor and time consumption is high

Engineering Contradiction:

Improvedefect rate prediction accuracyVSAvoidprediction time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent replaces manual mechanical analysis with an automated computational system that uses lithographic model parameters to predict defect rates. The system automatically extracts chemical parameters from lithographic simulations and applies defect rate models without human intervention, achieving both high accuracy and rapid prediction.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent creates a virtual copy of the lithographic process through calibrated lithographic models that simulate the actual manufacturing conditions. By analyzing parameters from this virtual representation, the system predicts defect rates without requiring physical trial runs, significantly reducing time while maintaining accuracy.

Inventive Principle:

Principle #26Copying

2Productivity

If manual defect analysis methods are used, then detailed examination can be performed, but the process is labor-intensive and inefficient

Engineering Contradiction:

Improvedefect prediction efficiencyVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a universal defect prediction system that handles multiple defect types (pinching, bridging, etc.) and various lithographic parameters through a single integrated computational framework. The system can analyze different IC design layouts and predict defect rates across multiple process conditions without requiring separate analysis tools for each case.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If accurate defect rate prediction is achieved through traditional methods, then yield can be optimized, but the process requires extensive manual effort and resources

Engineering Contradiction:

ImproveIC chip yieldVSAvoidmanufacturing process simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent performs defect rate prediction before actual IC manufacturing by using calibrated lithographic models and defect rate models to forecast potential issues. This preliminary analysis allows yield optimization decisions to be made during the design and process planning stages, avoiding the need for extensive trial manufacturing and reducing overall manufacturing complexity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11914306B2Predicting defect rate based on lithographic model parameters

Publication Date: 2024.02.27 SYNOPSYS INC

AI summary

A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.