Lithographic Illumination Optimization for IC Layout Yield

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Solution Overview

Problem

The challenge in lithographic processes is selecting optimal illumination conditions for transferring integrated circuit layouts across different lithographic systems without causing production losses due to printing difficulties, which arise from mismatched optical characteristics and system deficiencies.

Innovation Solution

A method that starts with an initial set of illumination conditions, calculates a local cost number for critical dimensions, aggregates these costs, and varies the conditions to select an optimal set, using cost functions that account for interdependencies in polygon patterns to ensure accurate circuit functionality and geometry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If illumination parameters are not carefully selected, then manufacturing yield decreases due to printing difficulties, but optimizing illumination conditions increases process complexity

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary optimization of illumination conditions by calculating cost numbers and selecting optimal parameters before actual production. This advance preparation prevents printing difficulties and yield loss during manufacturing, resolving the contradiction by addressing the problem before it occurs rather than during production.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses simulation models to create virtual copies of the lithographic process, allowing optimization of illumination conditions in a computational environment before applying them to actual manufacturing. This copying approach enables thorough optimization without increasing real-world process complexity.

Inventive Principle:
Principle #26Copying

2Manufacturing precision

If mask layout is tuned to specific lithographic system, then transfer characteristics improve, but adaptability to different systems decreases

Engineering Contradiction:
Improvetransfer characteristicsVSAvoidsystem adaptability
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent calculates cost numbers that quantify the sensitivity of transfer characteristics to illumination parameter changes. By identifying which parameters have the greatest impact on manufacturing yield, the system can optimize for specific lithographic systems while maintaining reasonable adaptability through parameter adjustment rather than complete retuning of the mask layout.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If cost number calculation is performed for yield prediction, then illumination setting optimization improves, but computational time increases

Engineering Contradiction:
Improveillumination setting optimizationVSAvoidcomputational time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent segments the calculation by focusing cost number evaluation on critical polygon patterns and hotspot regions rather than computing for the entire layout. This segmentation maintains accurate yield prediction for critical features while significantly reducing overall computational time and resources required.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8621401B2Method of selecting a set of illumination conditions of a lithographic apparatus for optimizing an integrated circuit physical layout
Publication Date: 2013.12.31 APPLIED MATERIALS INC
  • US8621401B2 patent drawing
  • US8621401B2 patent drawing
  • US8621401B2 patent drawing

AI summary

The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An initial set of illumination conditions is provided and a plurality of polygon patterns requiring illumination conditions critical for circuit functionality. For the initial set of illumination conditions a local cost number is calculated, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition. For each polygon pattern the cost numbers are aggregated; and the illumination conditions are varied so as to select an optimal set of illumination conditions having an optimized aggregated cost number. Polygon patterns are identified as predefined complex circuit elements and wherein the cost numbers are expressed as circuit element cost number functions that are individually associated with said identified complex circuit elements, so as to express circuit design intent. The cost number functions can further have interdependencies in multiple critical dimensions of the polygon patterns so as to take the two dimensional nature into account.