Litho-VIP Via Formation in Dielectric Pockets for High Density Interconnects
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Solution Overview
Problem
Current techniques for forming vertical interconnects in package substrates, such as self-aligned via (SAV) and zero misalignment via (ZMV) methods, require costly planarization processes and often necessitate each layer to include both pads and vias for signal propagation, limiting the achievable input/output density and increasing manufacturing costs.
Innovation Solution
The Litho-VIP method involves forming vias and conductive lines in a package substrate with a dielectric layer that includes pockets above pads, allowing for reduced pad sizes and eliminating the need for pads in every layer, while maintaining electrical connectivity through the use of clearance areas to prevent short circuits and optimize pitch between features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional via formation techniques (SAV or ZMV) are used, then vias can be formed with alignment to pads, but planarization processes are required which increase manufacturing costs and complexity
Solution Approach 1:
The patent applies preliminary action by forming pockets in the dielectric layer before via formation. These pockets pre-position the via openings at precise locations, eliminating the need for subsequent planarization processes while maintaining accurate via-pad alignment. The pockets are formed using lithography and etching to create recesses that guide via formation directly at the intended locations.
Solution Approach 2:
The patent extracts the planarization step from the traditional via formation process. By forming pockets that pre-establish via locations, the harmful planarization process is removed entirely. The pockets serve as pre-formed templates that eliminate the need for chemical mechanical polishing or other planarization techniques, thereby reducing manufacturing complexity and cost.
2Reliability
If each layer includes both pads and vias for signal propagation, then electrical connectivity is maintained, but the achievable input/output density per millimeter per layer is limited
Solution Approach 1:
The patent applies dimensionality change by utilizing vertical pockets in the dielectric layer to accommodate via structures. Instead of requiring pads at every lateral position on each layer, the via structures extend vertically through the dielectric pockets, enabling signal propagation through the third dimension. This allows intermediate layers to forgo pads while maintaining connectivity, thereby increasing I/O density.
Solution Approach 2:
The patent segments the electrical connectivity function across multiple dimensions. Rather than requiring complete pad-via structures at every layer, the connectivity is segmented such that pads are placed only where needed, and via structures in dielectric pockets handle the inter-layer connections. This segmentation reduces the number of pads required per layer, increasing overall density.
3Productivity
If pad sizes are reduced to increase I/O density, then more I/Os can be packed per millimeter, but misalignment between vias and pads increases
Solution Approach 1:
The patent uses preliminary action by forming pockets that pre-establish precise via locations before via formation. These pockets act as templates that ensure accurate via placement even when pads are small. The lithography process forms the pocket pattern with high precision, and subsequent via formation follows the pocket geometry, maintaining alignment without requiring large pads for tolerance compensation.
Solution Approach 2:
The patent introduces dielectric pockets as an intermediary structure between pads and vias. These pockets serve as a mediating element that defines via locations independently of pad sizes. The pocket walls provide physical guidance for via formation, ensuring precise alignment even when the adjacent pads are minimized for high density applications.
Data Source
AI summary
Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.