Lithographic Rounding Compensation in Semiconductor Device Modeling
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Solution Overview
Problem
Current semiconductor device layouts face challenges in accurately modeling device performance due to lithographic corner rounding effects, especially in miniaturized 45 nm technologies, where simplified design rules fail to account for the impact of landing pad spacing on device characteristics such as Ion, Ioff, and gate capacitance.
Innovation Solution
A computationally efficient method and system that models the effects of lithographic rounding on semiconductor transistor devices by determining the distance between landing pad features and active device edges, using polynomial functions to calculate changes in device width and current flow, and updating transistor model parameters to include deltaW values, thereby accurately simulating device parametrics like Ieff, Ion, and gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If landing pad spacing is decreased to increase device density, then device density is improved, but lithographic printing accuracy deteriorates due to corner rounding effects
Solution Approach 1:
The patent applies parameter changes by modifying the lithographic ground rules based on the specific spacing distance between landing pads and device edges. When the spacing parameter falls within a critical range (0.5L to 2.0L where L is the lithographic process resolution), adjusted ground rules are applied to account for corner rounding effects. This dynamic parameter adjustment resolves the contradiction by allowing denser layouts while compensating for lithographic inaccuracies through modified design constraints.
2Ease of manufacture
If simplified design rules are used for layout, then ease of manufacture is improved, but device performance modeling accuracy deteriorates
Solution Approach 1:
The patent implements dynamics by creating a conditional ground rule system that automatically adapts to different layout scenarios. Rather than using fixed simplified rules, the system dynamically selects appropriate ground rules based on the measured spacing between landing pads and device edges. This allows the manufacturing process to remain simple while achieving accurate performance modeling through context-dependent rule application.
Solution Approach 2:
The patent applies local quality by implementing different ground rule sets for different spatial contexts. When landing pad spacing is large, standard ground rules apply. When spacing falls into the critical range where corner rounding affects device performance, modified ground rules are applied locally to that specific region. This localized approach maintains overall layout simplicity while ensuring accuracy where it matters most.
3Quantity of substance
If landing pad to device distance is reduced, then device density is improved, but device performance accuracy deteriorates due to corner rounding influence
Solution Approach 1:
The patent applies preliminary anti-action by proactively compensating for corner rounding effects before they degrade device performance. The modified ground rules pre-adjust the landing pad dimensions and positioning to counteract the expected corner rounding that will occur during lithography. This preventive measure allows reduced spacing while maintaining device performance accuracy by anticipating and correcting for the rounding effect in advance.
Data Source
AI summary
A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature.