Lithographic Seam Layout for High-NA EUV Multi-Field ICs

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Solution Overview

Problem

The introduction of high-NA EUV lithography reduces maximum field size, necessitating multiple lithographic fields for larger die sizes, which poses challenges in design efficiency and layout due to seams between these fields.

Innovation Solution

Implementing a lithographic seam, or 'die mask zipper', that allows for multiple lithographic fields to be stitched together, using non-functional structures like registration marks and metrology features to maintain design flexibility and minimize area waste.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high-NA EUV lithography is used to reduce direct print patterning pitches, then manufacturing precision is improved, but device complexity increases due to multiple lithographic fields and seams

Engineering Contradiction:

Improvedirect print patterning pitchesVSAvoidmultiple lithographic fields and seams

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the lithographic field into multiple segments (first and second lithographic fields) that can be independently patterned and then stitched together. This segmentation allows each field to be optimized for high-NA EUV lithography while managing the complexity of large die sizes by breaking them into manageable portions with controlled seams between fields.

Inventive Principle:

Principle #1Segmentation

2Area of stationary object

If multiple lithographic fields are used for larger die sizes, then area of stationary object is improved, but loss of time increases due to additional exposures

Engineering Contradiction:

Improvedie sizeVSAvoidadditional exposures

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The patent incorporates preliminary action by pre-planning the seam locations and designing functional units that can be efficiently placed across seams. Registration marks and metrology features are pre-positioned to facilitate accurate stitching, reducing the time penalty associated with multiple exposures by streamlining the alignment and stitching processes.

Inventive Principle:

Principle #10Preliminary action

3Area of stationary object

If multiple lithographic fields are used for larger die sizes, then area of stationary object is improved, but productivity decreases due to seams between fields

Engineering Contradiction:

Improvedie sizeVSAvoiddesign efficiency and layout

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The patent applies local quality by allowing functional units to span across seams when beneficial for design efficiency, while maintaining seam-free regions where appropriate. The design methodology optimizes the placement of functional units relative to seams, enabling layout flexibility that maintains productivity despite the presence of multiple lithographic fields.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250112167A1Semiconductor design lithographic seam implementation methodology for advanced technologies

Publication Date: 2025.04.03 INTEL CORP

AI summary

An integrated circuit (IC) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. A functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. The IC device may include multiple such functional blocks spanning lithographic fields. The lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as registration marks and metrology structures. The multiple lithographic fields may be or include high numerical aperture extreme ultraviolet lithographic fields. The lithographic seam may interface with wafer finishing collaterals (such as guard rings).