Lithographically Defined Vias for Organic Package Substrate Scaling
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Solution Overview
Problem
Current semiconductor packaging technologies are limited by large via pad sizes due to laser drilling, which restricts input/output (I/O) density and requires expensive alternatives like silicon interposers or embedded silicon bridges to achieve higher routing densities.
Innovation Solution
The use of lithographic patterning to define vias instead of laser drilling, allowing for smaller via pads and improved alignment, resulting in higher I/O densities and increased throughput by enabling smaller line widths and spacings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling is used to create via openings, then via formation is achieved, but via pad sizes must be large (70 μm or larger) due to minimum feature size and misalignment
Solution Approach 1:
The patent changes the fundamental parameter of via formation from laser drilling to lithographic patterning. This enables via pad sizes to be reduced from 70 μm or larger to significantly smaller dimensions, directly resolving the contradiction between manufacturing precision and routing density by allowing more vias to be packed into the same area.
Solution Approach 2:
The patent replaces the mechanical laser drilling process with a lithographic patterning process. This substitution eliminates the minimum feature size constraints and misalignment issues inherent in laser drilling, enabling precise via formation with much smaller pad sizes and thereby increasing routing density.
2Productivity
If via pad sizes are reduced to increase routing density, then I/O density improves, but alignment precision deteriorates with laser drilling
Solution Approach 1:
The patent replaces laser drilling with lithographic patterning, which provides superior alignment precision. This enables via pad sizes to be reduced while maintaining or improving alignment accuracy, thereby increasing I/O density without sacrificing manufacturing precision.
Solution Approach 2:
By changing the via formation method from laser drilling to lithography, the patent achieves better alignment precision and enables smaller via pad sizes, simultaneously improving both I/O density and alignment precision rather than trading one for the other.
3Manufacturing precision
If UV lasers are used to reduce via opening size, then via pad size decreases, but throughput is greatly decreased
Solution Approach 1:
The patent replaces UV laser drilling with lithographic patterning. This substitution achieves smaller via opening sizes while maintaining high throughput, as lithography can pattern multiple vias simultaneously in a single process step, unlike sequential laser drilling.
Solution Approach 2:
The lithographic process merges the formation of multiple via openings into a single patterning operation, achieving both small via sizes and high throughput by processing many vias concurrently rather than sequentially as with laser methods.
4Productivity
If silicon interposers are used to achieve high routing density, then via formation precision improves, but cost increases significantly
Solution Approach 1:
The patent uses organic package substrates with lithographically defined vias instead of expensive silicon interposers. This approach achieves high routing density through process optimization rather than expensive materials, significantly reducing manufacturing cost while maintaining the desired routing capability.
Solution Approach 2:
The patent changes the substrate material from silicon to organic materials and the via formation method to lithography, achieving high routing density through parameter optimization rather than expensive materials, thereby reducing manufacturing cost while maintaining routing performance.
5Productivity
If embedded silicon bridges are used to reduce package size, then routing density improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the silicon bridge component entirely, achieving high routing density through lithographically defined vias in organic substrates alone. This eliminates the need for embedded silicon bridges and their associated manufacturing complexity while maintaining the routing density benefit.
Solution Approach 2:
The lithographic via formation process provides universal applicability across the entire package substrate, eliminating the need for separate silicon bridge components. This multi-functional approach achieves routing density improvement without adding structural complexity or manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach doubles or more the routing density without changing line and spacing requirements, reduces the need for additional layers, and lowers costs by using existing tooling and materials, while enabling more efficient via formation with various shapes and sizes in a single patterning operation.
Implementation Method 1
depositing a photoresist layer over the first dielectric layer and the via pad; patterning the photoresist layer to form a via opening over the via pad
Data Source
AI summary
Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.