Lithography-Aware Timing Analysis for Semiconductor Yield
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Solution Overview
Problem
Current electronic design automation methods for semiconductor chips face challenges in accurately calculating leakage and timing due to systematic and random variations, particularly the impact of lithography processes on transistor channel lengths and spacings, leading to insufficient yield and power consumption issues.
Innovation Solution
A method for performing lithography-aware leakage and timing analysis by determining neighborhood spacings between cells in a semiconductor circuit, characterizing the lithography process, and generating mappings to calculate leakage and delay based on these spacings, using a computer program product and system with processor and memory to execute instructions for generating leakage and delay information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If deterministic worst case analysis is used for power and timing calculations, then calculation simplicity is maintained, but yield becomes insufficient and power consumption is not accurately captured
Solution Approach 1:
The patent changes the analysis approach from deterministic worst-case parameters to statistical parameters including mean values, standard deviations, and percentiles. It introduces lithography-aware parameters that model the actual distribution of transistor characteristics and spacing variations, enabling accurate statistical timing and power analysis that reflects real manufacturing variability while maintaining computational efficiency through probabilistic methods.
2Measurement precision
If statistical analysis is used for timing and leakage analysis, then accuracy of power and timing calculations is improved, but computational complexity increases
Solution Approach 1:
The patent segments the chip into individual cells and transistors, analyzing each element's timing and leakage characteristics independently using statistical models. It divides the complex chip-level analysis into manageable cell-level computations, calculating mean and standard deviation parameters for each transistor and interconnect, then aggregating results to achieve accurate overall timing and power predictions without requiring exhaustive worst-case analysis of the entire chip.
Solution Approach 2:
The patent performs preliminary characterization of transistor and interconnect parameters by pre-calculating mean values, standard deviations, and percentile data for timing and leakage. This pre-characterization data is stored and reused during the actual timing and power analysis, avoiding the need to perform complex statistical computations on the entire chip during the analysis phase, thus reducing computational complexity while maintaining accuracy.
3Productivity
If lithography process variations are not considered, then analysis speed is maintained, but accuracy of timing and leakage predictions deteriorates
Solution Approach 1:
The patent introduces lithography-aware parameters that explicitly model systematic lithography variations such as defocus and overlay errors. It modifies the statistical parameters of transistor channel lengths and interconnect spacings to include lithography-induced variations, enabling accurate prediction of timing and leakage while maintaining analysis speed by using pre-characterized lithography effect models rather than performing full lithography simulation for each analysis case.
Data Source
AI summary
A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.