Lithography Bottleneck Identification via Time Data Segmentation
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Solution Overview
Problem
In semiconductor manufacturing, identifying bottlenecks in lithography operations is crucial for optimizing processing times and increasing efficiency, but existing methods lack a systematic approach to compare and analyze processing and transport times across various fabrication parameters and tools.
Innovation Solution
A method and software system that collects and parses wafer time log data from multiple lithography tools, classifies it based on fabrication parameters, and generates data displays to identify bottlenecks by comparing operation times, including processing and transport times, allowing for targeted improvements in tool performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple lithography tools with various unit operations are used to carry out patterning operations at different levels for different technologies and device types, then the versatility and capability to handle diverse fabrication parameters are improved, but the complexity of analyzing and comparing processing times across these tools increases
Solution Approach 1:
The patent segments the complex analysis task by dividing processing times into distinct unit operations (coat, soft bake, hard bake, develop, post-exposure bake, exposure, cool, adhesion enhancement, transport). This segmentation allows each operation to be analyzed independently while maintaining the ability to compare across multiple lithography tools and fabrication parameters, thus managing complexity while preserving versatility.
Solution Approach 2:
The patent introduces an intermediary data collection and analysis system that gathers processing time data from multiple lithography tools, standardizes the information across different fabrication parameters, and presents it in a unified format. This intermediary layer simplifies the comparison process by mediating between the diverse tool configurations and the analysis requirements.
2Productivity
If the number of unit operations and processing steps is increased to handle various device levels and technologies, then the manufacturing capability is improved, but the identification of bottlenecks becomes more difficult and time-consuming
Solution Approach 1:
The patent implements a feedback mechanism that continuously collects processing time data from each unit operation and automatically identifies bottlenecks by comparing actual performance against expected patterns. The system provides feedback on which operations are causing delays, enabling quick identification of bottlenecks even as the number of unit operations increases to handle diverse manufacturing capabilities.
Solution Approach 2:
The patent replaces manual bottleneck identification methods with an automated computer-based system that uses software to collect, analyze, and interpret processing time data. This substitution of mechanical/manual analysis with automated computational methods makes bottleneck detection efficient even when dealing with numerous unit operations and complex manufacturing capabilities.
3Productivity
If processing time at each operation is reduced to increase WPH output, then the manufacturing efficiency is improved, but the risk of creating new bottlenecks in other operations increases
Solution Approach 1:
The patent ensures continuous monitoring and analysis of all unit operations to maintain balanced processing times across the entire lithography sequence. By continuously tracking performance data from each operation (coat, bake, develop, exposure, cool, etc.), the system can identify and address bottlenecks before they disrupt the continuous flow of wafers, thereby maintaining high WPH output without creating new bottlenecks.
Solution Approach 2:
The patent employs dynamic analysis that adapts to changing conditions in real-time. As processing parameters and loads vary, the system dynamically identifies which operations are currently limiting throughput and provides targeted recommendations. This dynamic approach allows for optimizing WPH output by adjusting to actual operating conditions while preventing new bottlenecks from forming as the system state changes.
Data Source
AI summary
A method and a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded when a wafer is processed and transferred during lithography operations. The data is parsed and saved into an MES database. A report server accesses the database responsive to a query made of the database. A query may specify one or more fabrication parameters. The specified fabrication parameter or parameters is fixed and a data display is provided that compares times for processing and transferring wafers in various lithography operations used in the production of the semiconductor device and bottlenecks in lithography operations are identified by the comparative data.