Optical Lithography Edge Placement Error Correction
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Solution Overview
Problem
Conventional Optical Proximity Correction (OPC) and inverse-lithography technology models face challenges in computational complexity and efficiency, particularly in advanced optical lithography, where determining pre-distorted mask patterns for high-density feature placement on semiconductor wafers is difficult due to numerical complexity and convergence issues.
Innovation Solution
A method using non-linear optimization algorithms, such as the Broyden-Fletcher-Goldfarb-Shanno (BFGS) or steepest descent (SD) algorithms, to iteratively adjust the position of edge segments in mask patterns until the difference between simulated and drawn edge positions falls below a threshold, improving edge placement accuracy and reducing computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional OPC and ILT models are used to determine pre-distorted mask patterns, then manufacturing precision of wafer patterns is improved, but computational complexity and runtime increase significantly
Solution Approach 1:
The patent segments the mask pattern into discrete polygons and processes each polygon independently through the placement optimization algorithm. This segmentation allows the complex computational problem to be divided into smaller, more manageable sub-problems, reducing overall computational complexity while maintaining pattern accuracy
Solution Approach 2:
The patent transforms the continuous mask pattern adjustment problem into a discrete optimization problem by defining a cost function based on polygon placement parameters. By changing the problem representation from continuous distortion correction to discrete parameter optimization, the computational complexity is reduced while achieving comparable manufacturing precision
2Manufacturing precision
If conventional OPC and ILT models are used to determine pre-distorted mask patterns, then manufacturing precision of wafer patterns is improved, but runtime increases significantly
Solution Approach 1:
The patent performs preliminary segmentation of the mask pattern into polygons before optimization. By pre-processing the pattern data into discrete geometric elements, the subsequent optimization algorithm operates more efficiently, reducing runtime while maintaining the ability to achieve high manufacturing precision
Solution Approach 2:
The patent uses simplified polygon representations as disposable computational objects during the optimization process. These simplified geometric models enable faster computation compared to continuous pattern representations, reducing runtime without significantly compromising the final pattern accuracy
3Ease of operation
If target patterns are generated considering only logic requirements and electrical characteristics, then ease of design is improved, but manufacturing precision of wafer patterns deteriorates
Solution Approach 1:
The patent introduces an intermediary optimization step between design generation and mask fabrication. The placement optimization algorithm acts as a mediator that takes designer-friendly target patterns and automatically adjusts them to achieve lithographically optimal results, bridging the gap between design ease and manufacturing precision
Solution Approach 2:
The patent enables the design system to automatically optimize its own output patterns without requiring manual lithography expertise from designers. The automated placement optimization performs self-correction of pattern distortions, allowing designers to work at higher abstraction levels while the system handles the precision requirements
Data Source
AI summary
A method of determining the position of a first edge of a pattern in a mask used in fabricating an integrated circuit in which the first edge corresponds to a second edge associated with the pattern of a layout of the integrated circuit, includes, in part, dividing the edge into a multitude of segments, assigning a variable to each segment, applying a non-linear optimization algorithm to a current location of the first edge to determine an updated position of the first edge, determining a difference between the position of the second edge and a third edge corresponding to the updated position of the first edge and obtained by computer simulation of the mask pattern providing a model of the layout pattern when formed on a semiconductor wafer, and repeating the applying and the determining steps iteratively until the difference is smaller than a threshold value.