Triple-Pattern Lithography Layout Decomposition Validation
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Solution Overview
Problem
Triple-patterning lithography layout decomposition validation is a complex NP-complete problem, making it difficult to determine whether a semiconductor layout can be decomposed into three masks efficiently, especially due to the complexity of conflict graphs and potential decomposition violations.
Innovation Solution
The method involves generating a conflict graph representing the layout, simplifying it using techniques such as removing vertices connected to two or fewer edges, partitioning conflict graph portions, and applying rules to determine decomposition validity, allowing for the decomposition of the layout into three masks for triple-patterning lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple-patterning lithography layout decomposition validation is performed using traditional conflict graph analysis, then decomposition validity can be determined, but the computational complexity becomes NP-complete making it unsolvable in reasonable time
Solution Approach 1:
The patent segments the complex conflict graph analysis into multiple simpler validation rules (Rule 1 through Rule 5) that can be checked independently and efficiently. Each rule addresses a specific aspect of decomposition validity (e.g., odd-loop detection, vertex degree constraints, biconnected component analysis) rather than requiring exhaustive NP-complete conflict graph analysis, thereby reducing computational time while maintaining validation reliability
Solution Approach 2:
The patent introduces intermediary data structures and intermediate validation steps (such as biconnected component decomposition, vertex degree filtering, and rule-based preprocessing) that simplify the original conflict graph before applying comprehensive validation. These intermediaries break down the NP-complete problem into manageable sub-problems that can be solved efficiently
2Manufacturing precision
If the layout is decomposed into three masks for triple-patterning, then manufacturing precision for sub-45nm features is improved, but the process complexity and number of steps increase
Solution Approach 1:
The patent segments the lithography process into distinct validation phases (conflict graph generation, rule-based filtering, biconnected component analysis, and final validation) that can be executed systematically. This segmentation allows each phase to be optimized independently, reducing overall process complexity while achieving the required manufacturing precision for sub-45nm features
Solution Approach 2:
The patent performs preliminary validation actions before the actual triple-patterning lithography process, including conflict graph analysis, rule-based decomposition validation, and identification of potential violations. By detecting and resolving issues in advance, the patent prevents costly rework during manufacturing, thereby reducing process complexity while maintaining high precision
Data Source
AI summary
Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.