Lithography Mask Merging for Semiconductor Array and Periphery Patterning
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Solution Overview
Problem
The high cost of electronic devices is attributed to the need for multiple lithography steps, particularly the use of expensive newer equipment for patterning both array and periphery devices, which increases manufacturing costs.
Innovation Solution
A process is developed to form transistors and connections using a combination of photolithography tools, where advanced equipment is used for defining both array and periphery structures in fewer steps, with a mask formed by older equipment to define gates in the periphery and data lines in the array, thereby reducing the number of advanced lithography steps required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate lithography steps are used for patterning array and periphery devices, then design flexibility and signal quality are improved, but manufacturing cost increases due to multiple expensive lithography steps
Solution Approach 1:
The patent combines the patterning of array devices and periphery devices into a single lithography step by using a common mask layer that defines both array word lines and periphery gate structures simultaneously. This merging approach eliminates the need for separate lithography steps while maintaining the ability to create different device structures through selective etching and material deposition processes.
Solution Approach 2:
The mask layer serves multiple functions by simultaneously defining both array device features (word lines) and periphery device features (gates) in a single lithography step. This multi-functional mask approach allows one lithography tool to perform what previously required multiple specialized lithography steps, reducing manufacturing cost while maintaining design flexibility.
2Manufacturing precision
If newer, more capable lithography equipment is used for both array and periphery patterning, then patterning precision is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent uses a single mask layer that is consumed or modified during the patterning process to define both array and periphery structures. This disposable mask approach allows the use of less expensive lithography equipment while still achieving the required patterning precision, as the mask performs multiple functions in one step rather than requiring multiple expensive lithography tools.
Solution Approach 2:
The patent changes the processing parameters and material properties after the single lithography step to achieve different device characteristics. By using selective etching, different material depositions, and varied thermal processing, the same lithographically-defined pattern can produce both array devices and periphery devices with their respective precision requirements, reducing reliance on multiple high-end lithography tools.
3Reliability
If multiple lithography steps are used to accommodate differences between array and periphery devices, then device performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the manufacturing process into distinct material deposition and etching steps that follow the single lithography step. This allows different materials and processing conditions to be applied to different regions (array vs. periphery) while using a common lithographic pattern, thereby maintaining device performance differentiation without requiring multiple lithography steps.
Solution Approach 2:
The patent introduces intermediate processing steps (selective etching, material deposition, thermal processing) that act as mediators between the single lithography step and the final differentiated device structures. These intermediary processes enable the creation of both array and periphery devices with their specific performance characteristics from a single lithographically-defined pattern.
Data Source
AI summary
Disclosed are devices, among which is a device that includes a transistor and a contact. The transistor includes two terminals that may be formed in respective legs. The contact includes a first portion extending vertically, and a second portion extending perpendicularly with respect to the first portion. The second portion is wider than the first portion.