Matrix Reduction for Lithography Simulation via Graph Partitioning
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Solution Overview
Problem
The complexity of modern semiconductor circuit design, particularly in lithography simulation, is hindered by interactions between mask edges and electromagnetic radiation, making it difficult to calculate accurate semiconductor shapes due to Optical Proximity Correction (OPC) problems and the need for extensive lithography simulations.
Innovation Solution
A computer-implemented method that involves obtaining semiconductor design data, identifying target points and moveable mask edges, building an interaction graph, partitioning it into groups, and performing reduced lithography simulations to populate a Jacobian matrix, thereby reducing computational load and simulating interactions between mask edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If extensive lithography simulations are performed to account for mask edge interactions, then manufacturing precision is improved, but productivity deteriorates due to the large number of simulations required
Solution Approach 1:
The patent segments the set of moveable mask edges into multiple groups based on spatial proximity and interaction strength. By dividing the mask edges into near-field and far-field groups, the system performs detailed lithography simulations only for edges in the near-field that have significant interactions, while using simplified models for far-field edges. This segmentation reduces the total number of full lithography simulations required while maintaining manufacturing precision for critical features.
2Manufacturing precision
If interactions between all moveable mask edges are calculated, then manufacturing precision is improved, but device complexity increases due to the computational burden
Solution Approach 1:
The patent applies local quality by differentiating the level of analysis based on the location and interaction strength of mask edges. For mask edges with strong interactions (near-field), full lithography simulation is performed to capture complex electromagnetic effects accurately. For mask edges with weak interactions (far-field), simplified analytical models are used. This localized approach to simulation quality reduces overall computational complexity while maintaining manufacturing precision where it matters most.
Solution Approach 2:
The patent implements partial action by performing complete lithography simulations only for a subset of mask edges that have significant interactions, rather than simulating all mask edges equally. The system identifies critical near-field interactions and applies full simulation only to those cases, while using approximate models for less critical edges. This partial application of rigorous simulation reduces device complexity while maintaining sufficient manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of lithography simulations required, leading to a substantial decrease in computational resources needed for determining semiconductor fabrication shapes, enhancing the efficiency of semiconductor design analysis.
Implementation Method 1
Photolithography is commonly used to create structures in the chip. One photolithographic technique for forming a set of structures in a particular layer of a chip is to deposit a layer of material and then to coat the layer with a photosensitive material. A light is then shined through a mask, which possesses a variety of shapes to represent the desired structures, in order to selectively expose the areas of the photo-sensitive material not covered by the shapes in the mask.
Implementation Method 2
Because lithography uses electromagnetic radiation (EMR), such as visible light or ultraviolet light, to selectively expose areas of the chip through a mask
Implementation Method 3
If the dimensions of desired features get smaller than the wavelength of the EMR used, there can be interactions between the mask and the EMR, that impact the actual shapes of the exposed areas and make the exposed shapes different than the shapes on the mask.
Data Source
AI summary
A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector.