Lithography Overlay Simulation for Semiconductor Wafer Alignment
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges with overlay errors due to non-uniform stress and misalignment of patterns on wafers, which are exacerbated by shrinking ground rules and aggressive manufacturing processes, leading to increased costs and reduced accuracy when trying to minimize overlay errors without extensive overlay measurements.
Innovation Solution
A method and apparatus for simulating lithography overlay measurements, allowing for the testing of alternative measurement strategies and optimization of throughput by calculating alternative alignment and process control parameters, which can be used to generate simulated overlay data for improved process control and reduced measurement needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complete overlay measurements are performed on each semiconductor wafer at multiple positions, then measurement precision and yield rate improve, but productivity decreases due to slow measurement speed
Solution Approach 1:
The patent creates virtual copies of overlay measurements through simulation. A simulation model replicates the physical measurement process by generating synthetic overlay data based on process parameters, wafer deformation models, and pattern geometry. This allows multiple measurement scenarios to be evaluated without performing actual physical measurements, thereby maintaining measurement precision while eliminating the time penalty of repeated physical measurements.
Solution Approach 2:
The patent performs preliminary simulation of overlay measurements before actual manufacturing. By pre-calculating expected overlay errors using process control parameters and deformation models, the system identifies potential measurement issues and optimizes measurement strategies in advance. This preliminary action allows the system to plan the minimum necessary physical measurements, reducing overall measurement time while maintaining precision.
2Productivity
If the number of overlay measurement units is increased to distribute measurements, then productivity improves, but device complexity and cost increase
Solution Approach 1:
The simulation model serves multiple functions: it predicts overlay errors, evaluates measurement strategies, optimizes measurement positions, and validates process parameters. This single multi-functional simulation system replaces the need for multiple specialized overlay measurement units, as it can virtually perform all measurement evaluations that would otherwise require separate physical measurement devices.
Solution Approach 2:
The simulation model acts as an intermediary between process control and overlay measurement. Instead of directly increasing measurement capacity with more physical units, the simulation mediates by providing predictive information that reduces the actual measurement burden. It translates process parameters into expected overlay outcomes, allowing the system to minimize physical measurements while maintaining productivity.
3Productivity
If overlay measurements are reduced to increase throughput, then productivity improves, but measurement precision and reliability decrease
Solution Approach 1:
The simulation model incorporates feedback loops where simulated overlay results are compared against actual measurements and process specifications. This feedback continuously refines the simulation parameters and validation criteria, ensuring that the reduced set of physical measurements remains sufficient for maintaining precision. The system learns from each measurement cycle to optimize which measurements are most critical, preserving accuracy while minimizing measurement count.
4Productivity
If aggressive manufacturing processes are used to maintain productivity, then productivity improves, but overlay errors increase due to non-uniform stress
Solution Approach 1:
The simulation model performs preliminary assessment of overlay errors caused by aggressive manufacturing processes. By calculating expected stress distributions and wafer deformations before actual processing, the system identifies process parameters that may lead to excessive overlay errors. This allows pre-adjustment of process conditions or compensation strategies to counteract the harmful effects of aggressive manufacturing, maintaining both high productivity and overlay accuracy.
Data Source
AI summary
A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer; storing overlay parameters measured after the lithography step; calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.