Lithography Pattern Optimization via Topological Skeletons
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Solution Overview
Problem
The semiconductor manufacturing industry faces challenges in manufacturing integrated circuit designs due to shrinking feature sizes and increasing density, which exceed lithography capabilities, leading to manufacturing difficulties and yield issues, as existing design tools struggle to accurately analyze and adjust polygon edges within the capabilities of lithography.
Innovation Solution
The method involves transforming initial polygons into polygon topological skeletons and space topological skeletons, creating a connected network to perturb nodes based on a cost function that minimizes overlap and spacing specifications, reducing the complexity of analysis and achieving global optimality in spacing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polygon edge perturbations are performed using traditional design tools, then manufacturing yield can be improved, but the device complexity and processing time increase significantly
Solution Approach 1:
The patent segments the continuous polygon edge adjustment problem into discrete graph node perturbations. By representing polygon boundaries as graphs with nodes and edges, the optimization problem is divided into manageable units where only specific nodes are perturbed based on spacing violations, rather than adjusting all edge points continuously. This segmentation reduces the search space and computational complexity while maintaining manufacturing yield improvements.
Solution Approach 2:
The patent transforms the traditional two-dimensional continuous edge perturbation problem into a one-dimensional discrete graph node adjustment problem. By mapping polygon boundaries to graph structures and constraining perturbations to occur along graph edges rather than in continuous 2D space, the problem dimensionality is reduced. This transformation simplifies the optimization landscape and enables more efficient computation while achieving the same manufacturing yield goals.
2Productivity
If feature sizes are shrunk and density is increased to improve circuit functionality, then productivity is improved, but manufacturing precision deteriorates due to lithography limitations
Solution Approach 1:
The patent applies preliminary action by performing graph-based optimization on the layout design before it is sent to manufacturing. The system proactively identifies and corrects spacing violations by perturbing graph nodes to satisfy minimum spacing requirements, rather than waiting for manufacturing failures to occur. This pre-manufacturing optimization ensures that designs meeting density goals also meet lithography manufacturability constraints, preventing yield losses before production begins.
Data Source
AI summary
An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.