Lithography Stitching Alignment Marks for Large Semiconductor Dies
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Solution Overview
Problem
In the packaging of integrated circuits, existing methods face challenges in efficiently aligning and stitching together large semiconductor dies using multiple lithography masks, leading to potential misalignment and errors in conductive feature formation, which affects the size and accuracy of the resulting chip.
Innovation Solution
The method employs a multi-step lithography process with different masks to expose and develop photoresist in overlapping regions between active signal regions, creating stitching zones where conductive features are expanded beyond single reticle field limits, and uses mask overlay alignment marks within these zones to improve alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple lithography masks are used to stitch large semiconductor dies, then the chip area can be expanded beyond single reticle field limits, but alignment errors and misregistration occur between overlapping regions
Solution Approach 1:
Alignment marks are introduced as intermediary features between different reticle fields. These marks serve as reference points that mediate the alignment process, allowing precise registration between overlapping regions exposed by different lithography masks. The alignment marks act as a common language that enables accurate stitching across multiple fields.
Solution Approach 2:
Alignment marks are formed in advance during the lithography process, before the actual conductive features are patterned. This preliminary action establishes a reference framework that guides subsequent alignment operations, ensuring that when multiple reticle fields are stitched together, the overlapping regions will align correctly.
2Ease of operation
If conventional single-mask lithography is used, then alignment is simpler and faster, but the maximum chip size is limited by the reticle field size
Solution Approach 1:
The lithography process is segmented into multiple exposure steps, each covering a specific reticle field. By dividing the large chip area into manageable segments that can be exposed separately and then stitched together, the method overcomes the single reticle field size limitation while maintaining operational feasibility through the use of alignment marks.
Solution Approach 2:
The solution adds a temporal dimension to the lithography process by performing multiple sequential exposures instead of a single exposure. This multi-step approach in the time dimension allows coverage of larger areas while using the same spatial reticle field, effectively expanding the achievable chip area without requiring larger physical masks.
3Area of moving object
If multiple lithography exposures are performed to create stitching zones, then conductive features can be expanded across larger areas, but the process time and complexity increase
Solution Approach 1:
The lithography process maintains continuity by performing multiple exposures in sequence without interrupting the overall patterning objective. Each exposure step contributes directly to forming the complete conductive feature pattern across the entire chip area, ensuring that the useful action of pattern formation continues uninterrupted through all exposure steps.
Solution Approach 2:
Alignment marks are formed as a preliminary action that enables subsequent exposures to proceed efficiently. By establishing the alignment reference framework first, the method eliminates the need for time-consuming realignment procedures between exposures, thereby reducing overall process time despite multiple exposures being required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of larger chip areas by stitching conductive features across multiple reticle fields, reducing misalignment errors and enabling more extensive semiconductor device manufacturing with improved precision.
Implementation Method 1
exposing a first active signal region of photoresist to a first light-exposure using a first lithographic mask; and after exposing the first active signal region of photoresist to the first light-exposure, exposing a second active signal region of photoresist to a second light-exposure using a second lithographic mask
Data Source
AI summary
A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.