Synchronized Tile Computation for Large-Area Lithography Simulation

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Solution Overview

Problem

Conventional parallel computing solutions for large area lithography simulation face inefficiencies due to tile boundary inconsistencies, which arise from limited information exchange between neighboring tiles, leading to low simulation area efficiency and difficulties in stitching results, especially for advanced technology nodes beyond 5 nm.

Innovation Solution

A synchronized parallel computing architecture where a manager machine oversees overall algorithms, and worker machines exchange intermediate results to synchronize simulation steps, preventing tile boundary inconsistencies by treating the integrated circuit design layout as a whole and combining results symmetrically, allowing continuous information exchange during each iteration of processes like OPC and ILT.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional parallel computing solutions divide the layout into tiles for distributed processing, then computational efficiency is improved, but tile boundary inconsistencies arise due to limited information exchange between neighboring tiles

Engineering Contradiction:

Improvecomputational efficiencyVSAvoidsimulation accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent divides the large IC design layout into multiple smaller tiles that can be processed in parallel by different worker machines. This segmentation enables distributed computing while maintaining the ability to handle large area simulations that would be infeasible with a single processor.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The manager machine coordinates information exchange between neighboring tiles by collecting intermediate results from worker machines and distributing updated boundary information back to the appropriate tiles. This feedback mechanism ensures that tile boundary inconsistencies are resolved through iterative synchronization.

Inventive Principle:

Principle #23Feedback

2Speed

If tiles are processed independently in parallel, then processing speed is improved, but difficulties arise in stitching results together due to boundary inconsistencies

Engineering Contradiction:

Improveprocessing speedVSAvoidresult stitching

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The manager machine serves as an intermediary that mediates the stitching process between independently processed tiles. It collects intermediate results from worker machines, resolves boundary inconsistencies through coordinated information exchange, and combines the tile results into a unified simulation output.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary information exchange between neighboring tiles during the processing stages, resolving boundary inconsistencies before final result combination. This preliminary action prevents stitching difficulties by ensuring compatibility between adjacent tiles before they are merged.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If information exchange between neighboring tiles is limited, then parallel processing efficiency is improved, but simulation area efficiency decreases due to boundary inconsistencies

Engineering Contradiction:

Improveparallel processing efficiencyVSAvoidsimulation area efficiency

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The manager machine enables continuous information exchange between neighboring tiles throughout the iterative processing steps. This continuity ensures that boundary conditions are consistently updated and synchronized, maintaining simulation accuracy while allowing parallel processing to proceed efficiently without unnecessary idle time.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10915090B2Synchronized parallel tile computation for large area lithography simulation

Publication Date: 2021.02.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.