Optical Lithography Verification Filter for Defect Detection
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Solution Overview
Problem
Current lithography manufacturability verification techniques are inefficient and time-consuming, particularly in detecting defects in sub-lightwave pattern formations, due to their reliance on discrete evaluation points or contour generation methods, which are error-prone and data-intensive.
Innovation Solution
The method involves generating and applying filters, such as exposure latitude and feature latitude filters, to a lithography simulation to identify printable edges and detect defects, allowing for exhaustive full-chip verification with reduced computational time and improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If discrete evaluation points or contour generation methods are used for lithography verification, then measurement precision is improved, but productivity deteriorates due to time-consuming processing
Solution Approach 1:
The patent replaces traditional mechanical/computational contour generation and point-by-point evaluation methods with a filter-based optical verification approach. Filters are applied directly to the lithography simulation data to detect defects, substituting the complex mechanical verification process with a more efficient filtering operation that maintains precision while dramatically improving throughput
Solution Approach 2:
The patent changes the verification approach by transforming the problem from evaluating discrete points or generating contours to applying spatial filters with specific parameters (kernel sizes, threshold values) to the simulation data. This parameter-based filtering approach enables rapid defect detection without sacrificing measurement precision
2Manufacturing precision
If exhaustive full-chip verification is performed using traditional methods, then manufacturing precision is improved, but loss of time increases significantly
Solution Approach 1:
The patent substitutes traditional time-consuming contour generation and point evaluation mechanics with direct filter application to simulation data. This allows exhaustive full-chip verification to be performed rapidly by applying filters across the entire chip data structure without generating intermediate contours or evaluating discrete points
Solution Approach 2:
The patent performs verification actions preliminary to actual manufacturing by applying filters to lithography simulation data before fabrication. This preliminary filtering approach identifies potential defects early in the design phase, preventing time-consuming rework during manufacturing while maintaining precision
3Measurement precision
If traditional verification methods are used, then measurement accuracy is maintained, but device complexity increases due to data-intensive processing
Solution Approach 1:
The patent extracts only the essential verification function from complex contour generation and point evaluation systems. By applying filters directly to simulation data, it extracts defect information without the intermediate complexity of generating and processing contour data or evaluating numerous discrete points
Solution Approach 2:
The patent uses filter kernels that replicate the desired verification behavior across different regions of the chip. Instead of implementing complex verification logic for each evaluation point, simple filter templates are copied and applied throughout the data structure, reducing overall system complexity while maintaining measurement precision
Data Source
AI summary
An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at feast one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.