Last Level Cache Addressing for Uneven Memory Slices
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Solution Overview
Problem
Conventional memory systems face challenges in efficiently distributing memory traffic when the number of on-chip memory slices is not evenly divisible by the number of off-chip memory channels, leading to suboptimal performance and bandwidth utilization in graphics processing systems.
Innovation Solution
The implementation of addressing schemes that evenly distribute memory traffic across non-integer ratios of on-chip memory slices to off-chip memory channels using lookup tables, eliminating the need for a full crossbar switch and ensuring transparent access to memory clients, thereby maximizing LLC bandwidth and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional addressing schemes are used with non-integer ratios of slices to channels, then memory traffic distribution becomes uneven, but implementing a full crossbar switch would increase device complexity and chip area
Solution Approach 1:
The addressing logic is segmented into multiple independent lookup tables (one for each channel), where each table stores the mapping from slice indices to channel indices. This segmentation allows parallel evaluation of address mappings without requiring a complex centralized crossbar switch, thereby maintaining even memory traffic distribution while reducing device complexity.
Solution Approach 2:
Lookup tables serve as intermediary structures between the slice address space and channel interface. Instead of directly connecting all slices to all channels through a complex crossbar, the lookup tables mediate the address translation, enabling efficient and even memory traffic distribution with simpler logic.
2Productivity
If lookup tables are used for address mapping, then memory traffic is evenly distributed, but chip area and power consumption increase
Solution Approach 1:
The lookup tables are implemented with configurable size and granularity parameters that can be adjusted based on the specific non-integer ratio of slices to channels. By optimizing these parameters, the chip area required for the lookup tables is minimized while still achieving even memory traffic distribution and maximizing memory bandwidth utilization.
3Loss of time
If conventional addressing is used, then chip area is minimized, but memory access latency increases due to suboptimal traffic distribution
Solution Approach 1:
The lookup tables are pre-computed and pre-loaded with optimal address mappings during system initialization or manufacturing. This preliminary action ensures that during runtime, address translation can be performed efficiently without complex real-time calculations, thereby reducing memory access latency while maintaining even traffic distribution and high bandwidth utilization.
Data Source
AI summary
A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.