LLC Controller Bypass Logic for Large Memory Transactions
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Solution Overview
Problem
Large-sized memory transactions such as memset and memcopy operations cause pollution of L1-L3 caches, increase power consumption due to data movement, and accelerate silicon aging in processors.
Innovation Solution
The method involves determining if a memory transaction is of a preselected type and if its block size exceeds a certain threshold, allowing for an altered data path that reduces data movement, thereby bypassing the interconnect device and CPU, and utilizing the LLC controller to manage the transaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large-sized memory transactions (memset/memcopy) are performed through the processor using standard memory paths, then data can be accessed and manipulated, but cache pollution occurs, power consumption increases, and silicon aging accelerates
Solution Approach 1:
The patent introduces an intermediary component (memory management unit or bypass logic) that mediates large memory transactions between the processor and memory system. This intermediary detects when memset/memcopy operations target large memory blocks and redirects these transactions through an alternative path that bypasses the processor's cache hierarchy, thereby preventing cache pollution while still enabling the memory operations to complete
Solution Approach 2:
The patent segments memory transactions into two categories: small transactions that go through the processor's standard memory path (utilizing caches), and large transactions that are redirected through an alternative bypass path. This segmentation is achieved by detecting the size of the memory block being accessed and routing accordingly, allowing the system to optimize for both cache utilization and avoidance of cache pollution
2Ease of operation
If data is moved through the processor's cache hierarchy for large memory transactions, then memory operations can be performed, but power consumption increases due to redundant data movement
Solution Approach 1:
The intermediary component detects when a memory transaction involves a large memory block and redirects it through an alternative path that bypasses the energy-intensive cache hierarchy. This redirection occurs at the memory management unit or through bypass logic that recognizes the transaction type and size, enabling large memset/memcopy operations to complete with significantly reduced power consumption
3Productivity
If large memory transactions are processed through the processor core domain, then transactions can be executed, but silicon aging accelerates due to redundant transactions
Solution Approach 1:
The patent employs an intermediary memory management unit or bypass logic that intercepts large memory transactions before they enter the processor core domain. By detecting the transaction characteristics (memset/memcopy operations on large blocks), the intermediary redirects these transactions through an alternative path, thereby reducing the number of redundant transactions passing through the processor core and slowing down silicon aging
Solution Approach 2:
The system performs preliminary detection of memory transaction characteristics (type and size) before the transaction is fully processed through the processor. This preliminary action allows the system to proactively redirect large transactions through the bypass path, preventing them from causing accelerated aging in the processor core domain in the first place
Data Source
AI summary
Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.