Last-Level Cache Mesh Interconnect for Multi-Core Bandwidth
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Solution Overview
Problem
Existing multi-core processors face challenges in maintaining data transmission bandwidth among cores, last-level cache (LLC), and primary memory without affecting system performance.
Innovation Solution
Implementing a mesh-type interconnection structure that connects cache slices and primary storage node in a ring, with non-adjacent cache slices linked by fast paths, enhancing data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple cache slices are combined to form a large-capacity LLC, then the cache capacity is improved, but the data transmission bandwidth among cores, LLC, and primary memory deteriorates
Solution Approach 1:
The LLC is divided into multiple cache slices (first cache slice, second cache slice, etc.) that can be independently accessed. Each cache slice is connected to multiple cores through dedicated interconnection paths, allowing parallel data transmission operations without blocking other slices, thus maintaining high bandwidth while achieving large capacity
Solution Approach 2:
The patent introduces a multi-dimensional interconnection structure where cache slices are arranged in spatial dimensions and connected through multiple pathways. The first interconnection path connects adjacent cache slices while the second interconnection path connects non-adjacent cache slices, creating a three-dimensional communication architecture that increases bandwidth capacity without sacrificing cache capacity
2Device complexity
If a ring connection structure is used to connect primary storage node and cache slices, then the structure is simple, but the data transmission bandwidth is limited
Solution Approach 1:
The interconnection structure is segmented into multiple independent paths: a first interconnection path forming a ring connection for basic data transmission, and a second interconnection path providing additional connectivity between non-adjacent cache slices. This segmentation allows simultaneous operations on different paths, doubling the effective bandwidth while maintaining relatively simple individual path designs
Solution Approach 2:
The patent merges two interconnection approaches (ring connection and mesh connection) into a hybrid structure. The ring connection provides a simple baseline topology while the additional connections between non-adjacent cache slices merge mesh-like connectivity, combining the simplicity of ring structure with the high bandwidth capability of mesh structures
Data Source
AI summary
A processor with a high-capacity last-level cache is shown, which includes a plurality of cores, a primary storage node, a plurality of cache slices corresponding to the cores, and a mesh-type interconnection structure. The cache slices are combined as a last-level cache. The mesh-type interconnection structure connects the primary storage node and the cache slices in a ring, and connects at least two cache slices non-adjacent to each other in the ring.