LLM KV Cache Slot Mapping for Lower GPU Memory Overhead
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Solution Overview
Problem
The management of key-value caches in large language models is inefficient, leading to high GPU memory usage and impacting performance due to the need for repeated attention computations and inefficient memory management.
Innovation Solution
A virtual address space is divided into slots, and physical graphics memory is allocated based on capacity, maintaining a mapping relationship between virtual and physical memory blocks to simplify retrieval and reduce management complexity, thereby improving cache efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If KV cache is used to accelerate attention computing, then computing speed is improved, but GPU memory usage increases
Solution Approach 1:
The patent segments the KV cache into multiple slots, where each slot can independently store key-value pairs from different sequences. This segmentation allows the system to manage memory more efficiently by allocating slots dynamically based on actual needs rather than pre-allocating fixed memory for each sequence, thus reducing overall GPU memory consumption while maintaining fast access speeds.
Solution Approach 2:
The patent implements dynamic slot allocation and management, where slots can be allocated, released, and reused based on the actual batch processing requirements. This dynamic approach allows the KV cache to adapt to varying workloads, optimizing the balance between computing speed and memory usage by only allocating memory when needed and releasing it when not in use.
2Reliability
If KV cache stores all token key-value pairs, then attention computing accuracy is improved, but memory management complexity increases
Solution Approach 1:
By dividing the KV cache into discrete slots, the patent simplifies memory management operations. Each slot can be independently managed, allocated, and released, reducing the complexity of tracking and managing large contiguous memory blocks. This segmentation maintains all necessary token key-value pairs while making the management process more tractable and efficient.
Solution Approach 2:
The patent introduces a slot management mechanism that acts as an intermediary between the attention computing operations and the underlying GPU memory. This slot layer provides an abstracted interface for managing key-value pairs, simplifying the complexity of direct memory management while ensuring all necessary data is preserved for accurate attention computing.
3Adaptability or versatility
If sequence length is increased for longer prompts, then model reasoning capability is improved, but attention computing time increases
Solution Approach 1:
The patent pre-allocates KV cache slots for batch processing before actual computation begins. This preliminary action allows the system to prepare the memory structure in advance, so that when longer sequences are processed, the KV cache is already ready to receive and store the extended token key-value pairs without causing additional computational overhead during the attention computation phase.
Solution Approach 2:
The dynamic slot allocation mechanism allows the KV cache to efficiently handle variable sequence lengths. When longer prompts are input, the system can dynamically allocate additional slots as needed rather than being constrained by fixed memory allocations, enabling the model to process longer sequences with improved reasoning capability while minimizing the time penalty through efficient memory utilization.
Data Source
AI summary
Implementations of this specification provide key-value cache management, model reasoning, and data processing methods and apparatuses for large language models. In an implementation, a method comprises allocating a virtual memory block in a virtual address slot to newly-added token key-value data of a model reasoning request, in response to determining that a scheduling result of the model reasoning request indicates the model reasoning request is scheduled for execution, maintaining a mapping relationship between an occupied virtual address slot and a physical graphics memory block allocated to the model reasoning request, and copying the newly-added token key-value data to the physical graphics memory block.