Hardware-Aware LLM Training Scheduling on Heterogeneous GPU Clusters

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Solution Overview

Problem

Heterogeneous computing systems face inefficiencies due to varying hardware capabilities across nodes, leading to unequal processing speeds and inefficient data sharing, particularly in Large Language Model (LLM) training, where nodes with higher capabilities are underutilized and those with lower capabilities are overburdened, and data transfer using Remote Direct Memory Access (RDMA) is slow and costly.

Innovation Solution

Implement hardware-aware scheduling that accounts for node-specific capabilities and introduces cache-coherent interconnect memories like Compute Express Link (CXL) to optimize data sharing and reduce reliance on RDMA, utilizing a scheduling system that includes simulators, intra-node and inter-node schedulers, and evaluators to balance workload distribution and data flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hardware-aware scheduling is implemented to balance workload across heterogeneous nodes, then system efficiency and productivity improve, but device complexity and scheduling algorithm complexity increase

Engineering Contradiction:
Improvesystem efficiencyVSAvoidscheduling system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The scheduling system is divided into multiple independent components: a simulator that models system behavior, an intra-node scheduler that manages operations within individual nodes, an inter-node scheduler that coordinates between nodes, and an evaluator that assesses performance. This segmentation allows each component to handle specific aspects of the heterogeneous scheduling problem independently, improving overall system efficiency while managing complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The simulator performs preliminary analysis of the heterogeneous computing system's capabilities, hardware characteristics, and workload requirements before the actual scheduling begins. This preliminary action generates simulation results that inform the scheduling decisions, allowing the system to optimize workload distribution across heterogeneous nodes without requiring complex real-time calculations during execution.

Inventive Principle:
Principle #10Preliminary action

2Speed

If cache-coherent interconnect memories like CXL are introduced to optimize data sharing, then data transfer speed and system efficiency improve, but device complexity and interconnect architecture complexity increase

Engineering Contradiction:
Improvedata transfer speedVSAvoidinterconnect architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Cache-coherent interconnect memories such as CXL memory pools are introduced as intermediary components between GPU nodes and storage systems. These intermediaries provide a unified memory space that enables fast data sharing between heterogeneous nodes while maintaining cache coherence, effectively decoupling the complexity of direct peer-to-peer communication from the node architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If RDMA is used for data transfer between nodes, then data sharing capability is maintained, but transfer speed decreases and cost increases

Engineering Contradiction:
Improvedata sharing capabilityVSAvoiddata transfer speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system changes the fundamental parameters of data transfer by transitioning from RDMA-based direct memory access to cache-coherent interconnect memory access. This parameter change enables data transfers to occur through a unified memory space with higher bandwidth and lower latency, while maintaining the reliability of data sharing through cache coherence protocols that ensure consistent data visibility across all nodes.

Inventive Principle:
Principle #35Parameter changes

4Ease of operation

If homogeneous hardware assumption is made for simplicity, then system design and scheduling become easier, but heterogeneous systems suffer from underutilization of high-capability nodes and overburdening of low-capability nodes

Engineering Contradiction:
Improvescheduling easeVSAvoidnode utilization efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The scheduling system applies local quality by tailoring scheduling decisions to the specific characteristics of each heterogeneous node. The simulator and schedulers analyze individual node capabilities, hardware configurations, and performance metrics to generate customized scheduling policies for each node, ensuring that high-capability nodes receive more computationally intensive tasks while low-capability nodes handle lighter workloads, thereby optimizing overall system productivity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4693042A1Hardware-aware scheduling and data orchestration for balanced LLM training on heterogeneous GPU clusters
Publication Date: 2026.02.11 SAMSUNG ELECTRONICS CO LTD
  • EP4693042A1 patent drawingFigure 1
  • EP4693042A1 patent drawingFigure 2
  • EP4693042A1 patent drawingFigure 3

AI summary

A scheduling system is disclosed. The scheduling system may include a simulator (435) to process information regarding a heterogeneous computing system (305). An intra-node scheduler (440) may determine whether individual nodes should use a tensor parallel approach or a data parallel approach. An inter-node scheduler (445) may schedule operations between the nodes. An evaluator (450) may evaluate a performance of the heterogeneous computing system (305).