LLR Estimation Circuit for Flash Memory ECC Optimization
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Solution Overview
Problem
Existing flash memory storage devices face increased operation load due to the need for continuous determination of error characteristics to achieve optimal log likelihood ratio (LLR) for error checking and correcting (ECC) procedures, especially as the erase-program cycles increase, leading to inefficiencies in ECC decoding times.
Innovation Solution
A method and system for generating LLR in memory storage devices that reduces operation load by using a memory controller with an ECC circuit and LLR estimation circuit to calculate LLR based on read data, storage states, and storage errors, employing a logarithmic operation to generate an LLR that reduces iterative ECC procedure times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous determination of error characteristics is performed to achieve optimal LLR, then ECC performance is improved, but operation load increases
Solution Approach 1:
The patent pre-calculates and stores LLR values in a lookup table during manufacturing or initialization, based on theoretical error characteristics. This preliminary action eliminates the need for continuous real-time determination of error characteristics during normal operation, significantly reducing the operation load while maintaining accurate LLR values for optimal ECC performance.
Solution Approach 2:
The patent creates a static copy of the error characteristic data (LLR values) in a lookup table, which can be repeatedly accessed without recalculation. This copying approach allows the system to use pre-determined LLR values for multiple ECC operations, avoiding the repeated computational burden of determining error characteristics from scratch each time.
2Loss of time
If accurate LLR is obtained through training samples, then iteration times in ECC procedure are reduced, but system load increases
Solution Approach 1:
The patent performs the time-consuming LLR calculation and validation process in advance during manufacturing or initialization, storing the results in a lookup table. This preliminary action ensures that accurate LLR values are readily available during normal ECC operations, reducing iteration times without imposing continuous system load.
Solution Approach 2:
The patent makes the system self-sufficient by embedding the pre-calculated LLR values directly in the device's lookup table, eliminating the need for external training sample processing or continuous system resources to maintain accurate LLR values. The system serves itself with pre-prepared data.
3Measurement precision
If error characteristics are continuously determined to adapt to erase-program times, then LLR accuracy is improved, but processing overhead increases
Solution Approach 1:
The patent addresses different erase-program time scenarios by pre-calculating LLR values for various conditions and storing them in the lookup table. This preliminary action for multiple scenarios ensures that the appropriate accurate LLR can be selected based on current conditions without real-time calculation, maintaining LLR accuracy while avoiding processing overhead.
Solution Approach 2:
The patent creates multiple LLR values in the lookup table corresponding to different erase-program time parameters. By changing the parameter (selecting different pre-calculated LLR values based on erase-program times), the system maintains high LLR accuracy without the need for continuous determination processes that would reduce processing efficiency.
Data Source
AI summary
A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.