LLR Lookup Table Switching for Single-Read NAND Error Correction
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Solution Overview
Problem
Existing error correction methods for solid state memory systems, such as those using log likelihood ratio (LLR) lookup tables (LUTs), are inefficient due to the need for re-read operations to correct errors, which introduce significant performance penalties and delays, especially when dealing with asymmetric bit errors.
Innovation Solution
Implementing multiple LLR-LUTs configured to address different degrees of asymmetry in bit errors during a single read operation, allowing iterative decoding with multiple LUTs to be applied sequentially without resetting the decoder, thereby improving error correction efficiency and reducing the need for re-reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single LLR-LUT is used for error correction during a read operation, then the decoding process is simple and fast, but it fails to correct asymmetric bit errors effectively, requiring re-read operations that introduce delays
Solution Approach 1:
The patent divides the error correction process into multiple segments by using multiple LLR-LUTs (Lookup Tables) instead of a single LUT. Each LUT is configured to handle different degrees of asymmetric bit errors, allowing the system to segment the error correction task into specialized handling paths that can be tried sequentially without resetting the decoder.
Solution Approach 2:
The system dynamically selects and switches between different LLR-LUTs based on the decoding success or failure. When the first LUT fails to decode, the system transitions to trying the next LUT in sequence, creating a dynamic error correction process that adapts to the actual error conditions without requiring a re-read operation.
2Reliability
If multiple LLR-LUTs are used to address different degrees of asymmetric errors, then error correction effectiveness improves, but the decoding process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple LLR-LUTs with different asymmetry parameters before the actual decoding process. This preparation allows the system to quickly try different error correction approaches without complex real-time calculations, reducing the operational complexity while maintaining multiple correction capabilities.
Solution Approach 2:
The system changes parameters by using multiple LLR-LUTs with different configured asymmetry parameters. Each LUT represents a different parameter configuration for handling asymmetric errors, allowing the system to adjust the error correction approach by selecting different LUTs based on the observed error patterns.
3Reliability
If re-read operations are performed to correct errors that fail initial decoding, then error correction can be achieved, but significant performance penalties and delays are introduced
Solution Approach 1:
The patent merges multiple error correction attempts into a single read operation by sequentially trying multiple pre-configured LLR-LUTs within the same decoding cycle. This combining of correction strategies eliminates the need for separate re-read operations, maintaining productivity while achieving reliable error correction.
Solution Approach 2:
The system maintains continuity of useful action by keeping the decoder running and continuously trying different LUTs without interrupting the read operation. This continuous decoding process with multiple LUT attempts ensures that error correction happens within the original read timeframe, preventing throughput degradation.
Data Source
AI summary
Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.