LLR Mapping Tables for Low-Latency Flash LDPC Decoding
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Solution Overview
Problem
Flash storage systems face errors due to deterioration over program or erase cycles and high temperatures, with existing LDPC decoding methods being resource intensive and latency-prone.
Innovation Solution
Implementing multiple LLR mapping tables to generate LLR values for finite-precision LDPC decoders, optimizing them to avoid saturation-related artifacts and noise floors, and dynamically selecting tables based on decoding attempts and storage media conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative message-passing decoding is used to achieve near-optimal performance, then error correction capability is improved, but power consumption and decoding latency increase
Solution Approach 1:
The patent segments the LLR value representation into multiple tables, each handling different magnitude ranges. This segmentation allows the decoder to use simpler operations for common cases while maintaining accuracy for edge cases, reducing overall computational complexity and power consumption during iterative decoding
Solution Approach 2:
The patent changes the parameter representation by using multiple LLR mapping tables with different precision levels instead of a single uniform precision. This allows the system to adaptively adjust the effective precision based on the input magnitude, reducing unnecessary computational operations and lowering power consumption while maintaining error correction capability
2Reliability
If iterative message-passing decoding is used to achieve near-optimal performance, then error correction capability is improved, but decoding latency increases
Solution Approach 1:
By segmenting the LLR processing into multiple specialized tables, the patent enables faster lookup and processing operations during each iteration. The segmentation allows the decoder to quickly determine which table to use based on input magnitude, reducing the time per iteration while maintaining the same number of iterations needed for convergence
Solution Approach 2:
The patent performs preliminary organization of LLR values into multiple mapping tables during system initialization. This preliminary action allows the decoder to directly lookup pre-computed values during iterative decoding, avoiding complex real-time calculations and significantly reducing decoding latency per iteration
3Measurement precision
If LLR mapping tables are optimized for finite-precision decoders to avoid saturation artifacts, then decoding accuracy is improved, but system complexity increases
Solution Approach 1:
The patent divides the LLR processing space into multiple segments, each handled by a dedicated mapping table. This segmentation prevents saturation artifacts by ensuring each table handles a specific magnitude range with appropriate precision, while the modular table structure keeps system complexity manageable through organized, reusable components
Solution Approach 2:
The patent applies local quality by giving different precision characteristics to different parts of the LLR value range. Each mapping table is optimized for its specific range, providing high precision where needed while using coarser representation where acceptable, thereby improving overall decoding accuracy without uniformly increasing complexity across all operations
Data Source
AI summary
Read data associated with Flash storage is received. One of a plurality of LLR mapping tables is selected and a set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has a same finite precision as a finite-precision low-density parity-check (LDPC) decoder. Error-corrected read data is generated using the set of LLR values, where the finite-precision LDPC decoder has the same finite precision as the set of LLR values. The error-corrected read data is output.