LLR Mapping Tables for Low-Latency Flash LDPC Decoding

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Solution Overview

Problem

Flash storage systems face challenges in efficiently decoding low-density parity-check (LDPC) codes due to resource-intensive methods for generating log-likelihood ratio (LLR) values, which result in high latency and power consumption, especially as the storage medium deteriorates over time and with increasing temperature.

Innovation Solution

Implementing multiple LLR mapping tables to generate LLR values for finite-precision LDPC decoders, optimizing them to avoid saturation-related artifacts and noise floors, and dynamically selecting the appropriate table based on decoding attempts and storage medium conditions to reduce errors and improve decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional LLR generation methods are used, then decoding accuracy is maintained, but power consumption and decoding latency increase

Engineering Contradiction:

Improvedecoding accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent divides the LLR generation process into multiple discrete mapping tables, each optimized for specific storage medium conditions. Instead of using a single complex generation method, the system segments the solution into multiple specialized mappings that can be selectively applied, reducing overall computational power while maintaining accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameters of LLR mapping tables based on storage medium conditions such as temperature and cycle count. By adapting the mapping table parameters to current medium state, the system achieves accurate decoding with reduced computational complexity compared to fixed-parameter traditional methods.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If traditional LLR generation methods are used, then decoding accuracy is maintained, but decoding latency increases

Engineering Contradiction:

Improvedecoding accuracyVSAvoiddecoding latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary organization of LLR mapping tables based on expected storage medium conditions. By pre-configuring multiple mapping tables for different conditions, the system avoids complex real-time calculations during decoding, thereby reducing latency while maintaining accuracy through appropriate table selection.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically changes mapping table parameters based on storage medium state, allowing optimal decoding performance for each condition without requiring exhaustive search or complex adaptive algorithms, thus reducing decoding latency.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If multiple LLR mapping tables are implemented, then decoding efficiency improves, but device complexity increases

Engineering Contradiction:

Improvedecoding efficiencyVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent creates mapping tables that serve multiple functions - each table is designed to handle specific ranges of storage medium conditions while maintaining compatibility with the overall decoding framework. This multi-functionality allows the system to improve decoding efficiency across various conditions without proportionally increasing complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The mapping tables act as intermediaries between the raw storage medium state and the LDPC decoder. By introducing these intermediate lookup structures, the system simplifies the decoding process for each condition while managing overall complexity through structured organization of the multiple tables.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Reliability

If LLR mapping tables are optimized for specific conditions, then error mitigation improves, but adaptability decreases

Engineering Contradiction:

Improveerror mitigationVSAvoidcondition adaptability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the storage medium condition space into multiple discrete categories, each with its own optimized mapping table. This segmentation allows specialized optimization for each condition type while maintaining overall adaptability through the collection of segmented solutions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically selects and switches between different mapping tables based on real-time storage medium conditions. This dynamic adaptation allows the system to maintain high error mitigation performance across varying conditions by always using the most appropriate optimized table for the current state.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11641213B2Log-likelihood ratio mapping tables in flash storage systems

Publication Date: 2023.05.02 NANJING TENAFE ELECTRONIC TECHNOLOGY CO LTD

AI summary

Read data associated with Flash storage that is in a Flash storage state is received. One of a plurality of log-likelihood ratio (LLR) mapping tables is selected based at least in part on: (1) the Flash storage state and (2) a decoding attempt count associated with a finite-precision low-density parity-check (LDPC) decoder. A set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has a same finite precision as the finite-precision LDPC decoder. The finite-precision LDPC decoder generates the error-corrected read data using the set of LLR values and outputs it.