LMS Echo Canceller Step Size via Binary Shift
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Solution Overview
Problem
Existing echo cancellers, particularly those using least mean squares (LMS) algorithms, face computational intensity and precision issues due to division operations and limited processor capabilities, leading to suboptimal performance and difficulty in achieving deep convergence in resource-constrained digital signal processing applications.
Innovation Solution
The method involves comparing an excitation signal power estimate to a reference power level to determine a shift adjustment, allowing the step size to be applied through binary shifts rather than mathematical computations, eliminating the need for division and reducing computational complexity while maintaining precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If division operations are used to apply step size in LMS echo cancellers, then precision can be maintained, but computational complexity increases and processing efficiency decreases
Solution Approach 1:
The patent substitutes the mathematical division operation with a binary shift operation. Instead of computing step_size = reference_step_size * (reference_power / current Power), the patent uses step_size = reference_step_size << shift_amount, where shift_amount is determined by comparing current power to reference power. This replacement of division with bit shifting dramatically reduces computational complexity while preserving precision.
Solution Approach 2:
The patent changes the representation and computation method of the step size parameter. By expressing the step size adjustment as a power-of-two scaling factor (through binary shifts) rather than through direct division, the patent transforms a computationally intensive operation into a simple bitwise operation that maintains numerical precision.
2Measurement precision
If conventional mathematical computations are used to apply step size, then precision is maintained, but processor load increases and processing efficiency decreases
Solution Approach 1:
The patent replaces conventional mathematical computations (multiplication and division) with binary shift operations. The step size application is transformed from floating-point or fixed-point arithmetic into integer bit shifting, which is natively supported by processors and executes significantly faster, thereby improving processing efficiency without sacrificing precision.
Solution Approach 2:
The patent uses a simplified, computationally inexpensive method (binary shifting) to achieve the step size adjustment function. This approach trades the complexity of precise mathematical computation for a simpler, faster operation that is sufficiently accurate for the application, effectively using a 'cheaper' computational method to achieve the same functional goal.
3Reliability
If LMS algorithms are implemented in resource-constrained digital signal processing applications, then echo cancellation functionality is achieved, but deep convergence becomes difficult to obtain due to computational limitations
Solution Approach 1:
The patent replaces computationally intensive division operations with binary shift operations, enabling LMS algorithms to run efficiently on resource-constrained digital signal processors. This substitution reduces the processor load and computational complexity, allowing the algorithm to converge deeply even in embedded systems with limited processing power.
Solution Approach 2:
The patent implements a dynamic step size adjustment mechanism that adapts to changing signal conditions. By comparing current signal power to a reference power level and adjusting the step size accordingly using binary shifts, the algorithm maintains optimal convergence behavior across varying operational conditions, enabling deep convergence in resource-constrained environments.
Data Source
AI summary
Disclosed is an improved method and apparatus for estimating and applying a step size value for a least mean squares echo canceller. A power estimate of an excitation signal is compared to a reference power level to determine a shift adjustment. The shift adjustment is added to a reference shift amount to determine a shift amount. The product of an excitation signal and an error signal is then calculated and the product is stored in a memory register comprising a plurality of bits. The bits stored in the memory register are shifted either left or right based upon the shift amount. The shift adjustment may be based in part upon the ratio of the excitation signal power estimate and the reference power level.