LO Divider Circuit Switching for Accurate Duty Cycle Control
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Solution Overview
Problem
Existing divide-by-2 circuits for generating local oscillator signals in radios face issues with shoot through currents, high impedance nodes, and inaccurate duty cycle, which affect power consumption and noise rejection.
Innovation Solution
A divider circuit design that includes a first output section with switches configured to prevent simultaneous coupling or decoupling of the output node to both voltages, using clocked switches with equal rising and falling edge delays to generate digital signals with precise 25%, 50%, or 75% duty cycles, reducing shoot through currents and high impedance nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional divide-by-2 circuits are used to generate LO signals, then the circuit can operate with simple structure, but shoot through currents occur causing increased power consumption
Solution Approach 1:
A control switch is introduced as an intermediary element between the first and second switches. This control switch is activated by a control signal that is phase-shifted relative to the clock signal, and it selectively couples or decouples the output node from both the first and second voltages. This intermediary control mechanism prevents the simultaneous conduction of the first and second switches, thereby eliminating shoot through currents and reducing power consumption.
2Object-affected harmful factors
If conventional divide-by-2 circuits are used, then the circuit design is simple, but high impedance nodes are created making the circuit susceptible to noise
Solution Approach 1:
The control switch acts as an intermediary that ensures the output node is always properly connected to either the first voltage, the second voltage, or both simultaneously during transition periods. By preventing the output node from entering a high impedance state where it is decoupled from both voltages, the control switch eliminates noise susceptibility without requiring complex shielding or filtering circuits.
3Measurement precision
If conventional divide-by-2 circuits are used, then the circuit operates with basic components, but duty cycle accuracy is poor
Solution Approach 1:
The control switch is governed by a control signal that is derived from the clock signal but phase-shifted by a specific amount (e.g., 45 degrees). This phase-shifted feedback mechanism ensures that the control switch activates at the appropriate moment to prevent simultaneous switching of the first and second switches, thereby achieving accurate duty cycle control (25%, 50%, or 75% as required) while maintaining a relatively simple circuit structure.
4Measurement precision
If AND gates are used to generate 25% duty cycle LO signals as in prior art, then the desired duty cycle is achieved, but extra power is consumed and noise is added at high frequencies
Solution Approach 1:
The patent replaces the mechanical/logic gate-based approach (using AND gates) with an electronic switching approach. Instead of using AND gates to combine signals to achieve 25% duty cycle, the invention uses a control switch that is timed to activate during specific portions of the clock cycle. This electronic timing mechanism achieves the same duty cycle precision while consuming less power and introducing less noise, as it avoids the continuous operation and high-frequency susceptibility of AND gates.
Data Source
AI summary
A divider circuit and method for generating one or more digital signals is presented. The circuit has a first output section for generating a first digital signal. There is a first output section with an output node to output the first digital signal, and a plurality of switches with one or more control switches. The plurality of switches selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal. The or each control switch is prevents at least one of (i) the output node being coupled to the first and second voltages simultaneously and (ii) the output node being decoupled from both the first and second voltages simultaneously.